Intel 815 manual Reserved, Ring Buffer Valid

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Dword	Bit	Description
Offset
0	31:21	Reserved.
	20:3	Tail Pointer : Programmable Qword Offset in the ring buffer (20:3 is used by the
		hardware).
	2:0	Reserved.
1	31:2	Head pointer: Hardware maintained DWord Offset in the ring buffer (20:2 is used by
		the hardware, Bits 31:21 are incremented whenever the head pointer wraps from the
		end to the start of the ring buffer <> Wrap Count).
	1:0	Reserved.
2	31:26	Reserved
	25:12	Starting Address: Programmable 4 KB page aligned address of the buffer. This is a
		physical address (no GTT translation).
	11:0	Reserved
3	31:21	Reserved
	20:12	Buffer Length: Programmable length of the ring buffer in 4 KB Pages
		(Maximum = 2 MB, x000 = One 4 KB Page)
	11:3	Reserved
	2:1	Automatic Report Head pointer: Report happens when the Ring DMA crosses
		64 KB or 128 KB boundary.
		X0 = No report
		01 = Report every 16 pages (64 KB)
		11 = Report every 32 pages (128 KB).
	0	Ring Buffer Valid:
		0 = Disabled
		1 = Enabled.

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