Intel 815 manual 4. GR02Color Compare Register, 5. GR03Data Rotate Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.3.4.GR02Color Compare Register

I/O (and Memory Offset) Address:				3CFh (Index=02h)
Default:				0Uh (U=Undefined)
Attributes:				Read/Write
7				4	3	2	1	0
			Reserved (0000)		Color	Color	Color	Color
					Compare	Compare	Compare	Compare
					Plane 3	Plane 2	Plane 1	Plane 0
		Bit			Description
	7:4		Reserved. Read as 0s.
	3:0		Color Compare Plane [3:0]. When the Read Mode bit (bit 3) of the Graphics Mode Register (GR05) is
			set to select Read Mode 1, all 8 bits of each byte of each of the 4 memory planes of the frame buffer
			corresponding to the address from which a processor read access is being performed are compared to
			the corresponding bits in this register (if the corresponding bit in the Color Don’t Care Register (GR07) is
			set to 1). The value that the processor receives from the read access is an 8-bit value that shows the
			result of this comparison, wherein value of 1 in a given bit position indicates that all of the corresponding
			bits in the bytes across all of the memory planes that were included in the comparison had the same
			value as their memory plane’s respective bits in this register.

9.3.5.GR03Data Rotate Register

I/O (and Memory Offset) Address:				3CFh (Index=03h)
Default:				0Uh (U=Undefined)
Attributes:				Read/Write
7			5	4	3	2	0
			Reserved	Function Select			Rotate Count
		Bit		Description
	7:5		Reserved. Read as 0s.
	4:3		Function Select. These bits specify the logical function (if any) to be performed on data that is meant to
			be written to the frame buffer (using the contents of the memory read latch) just before it is actually
			stored in the frame buffer at the intended address location.
			00 = Data being written to the frame buffer remains unchanged, and is simply stored in the frame buffer.
			01 = Data being written to the frame buffer is logically ANDed with the data in the memory read latch
			before it is actually stored in the frame buffer.
			10 = Data being written to the frame buffer is logically ORed with the data in the memory read latch
			before it is actually stored in the frame buffer.
			11 = Data being written to the frame buffer is logically XORed with the data in the memory read latch
			before it is actually stored in the frame buffer.
	2:0		Rotate Count. These bits specify the number of bits to the right to rotate any data that is meant to be
			written to the frame buffer just before it is actually stored in the frame buffer at the intended address
			location.

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