Intel Error Identity, Mask and Status Registers, Table Error handling in Intel 815 Chipset

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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16.2.6.Error Identity, Mask and Status Registers

The Error Identity, Mask, and Status registers have the following bit descriptions. The master error bit in the ISR and IIR register will be set when the OR of the unmasked (with a zero in the corresponding mask register bits) error status bits is true.

16.2.6.1.Page Table Error handling in Intel® 815 Chipset

Page table errors can be caused by accessing graphics aperture space when:

1.The page table is not enabled.

2.Attempting to access local memory in a UMA system.

3.Attempting to access a page table entry, which does not have the valid bit set.

4.The location of the page table is in restricted region (e.g., SMM space) in memory.

For cycles initiated from the graphics host, TLB error should not cause the system to hang.

TLB error is flagged only for a write. For the write cycle with the TLB error and for all subsequent write cycles, byte enables are masked. If local memory is accessed in UMA system, the cycle is forwarded to system memory and completed with masked byte enables. For a write TLB error, error registers should be appropriately set.

Graphics memory reads do not cause any side-effects. Hence, all reads with a TLB error are allowed to complete. Note that no error condition will be set in the Error registers for a read TLB error.

Irrespective of the cycle being a read or a write, if the location of page table is in a restricted region, a page table error will be set. This error is not resettable.

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