Intel 815 manual DRAMCH-DRAM Control High

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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18.3.DRAMCH—DRAM Control High

Address offset :				03002h
Default value :				08h
Access :				Read / write
Size :				8 bit
7			5	4	3	2	0
			Reserved	DRAM Refresh Rate			Special Mode Select
		Bit		Description
	7:5		Reserved
	4:3		DRAM Refresh Rate (DRR). DRAM refresh is controlled using this field. Disabling refresh results in the
			eventual loss of DRAM data, although refresh can be briefly disabled without data loss. The field must
			be set to normal refresh as soon as possible once DRAM testing is completed.
			00 = Refresh Disabled
			01 = Refresh Enabed (default)
			11 = Reserved
			10 = Reserved
	2:0		Special Mode Select (SMS). These bits select special SDRAM modes used for testing and initialization.
			Note that the NOP command must be programmed first before any other command can be issued.
			000 = Normal SDRAM mode (Normal, default).
			001 = NOP Command Enable (NCE). This state forces cycles to DRAM to generate SDRAM NOP
			commands.
			010 = All Banks Precharge Command Enable (ABPCE). This state forces cycles to DRAM to generate
			an all banks precharge command.
			011 = Mode Register Command Enable (MRCE). This state forces all cycles to DRAM to be converted
			into MRS commands. The command is driven on the MA[11:0] lines. MA[2:0] correspond to the
			burst length, MA[3] corresponds to the wrap type, and MA[6:4] correspond to the latency mode.
			MA[11:7] are driven to 00000 by The GMCH,
			The BIOS must select an appropriate host address for each row of memory such that the right
			commands are generated on the MA[6:0] lines, taking into account the mapping of host
			addresses to local memory addresses.
			100 = CBR Cycle Enable (CBRCE). This state forces cycles to DRAM to generate SDRAM CBR refresh
			cycles.
			101 = Reserved.
			11X = Reserved.

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