Intel 815 manual Resetting the Page Table Error

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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16.2.6.2.Resetting the Page Table Error

The page table error will be reset every time a write cycle is generated to bit 15 of the Interrupt Identity register (IIR), independent of the setting of the bit in the IMR or the IER. Resetting the page table error should cause the subsequent write cycles to be completed without masking of the byte enables. Note that a TLB error due to locating a page in system memory can never be cleared.

15		6	5	4	3	2	1	0
	Reserved		MM/LM	Page	Display or	Reserved	Reserved	Instruction
			Refresh	Table	Overlay			Parser
			timer error	Error	under run			Error
Bit					Description
15:6	Reserved
5	MM/LM Refresh Timer Error:
	1	= Indicates a refresh overrun.
4	Page Table Error:
	1	= Page table error
	0	= Cleared by a processor write of a one to the error identity bit.
3	Display or Overlay Under run:
	1	= Display or overlay under run error
	0	= Cleared by a processor write of a one to the Error identity bit. See display and overlay status
		registers to determine source of the error.
2	Reserved
1	Reserved
0	Instruction Parser Error: The Instruction Parser encounters an error while parsing an instruction.
	1	= Error
	0	= Cleared by a processor write of a one to the Error identity bit.

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