Intel 815 manual Attribute Controller Registers, ARXAttribute Controller Index Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.4.Attribute Controller Registers

Unlike the other sets of indexed registers, the attribute controller registers are not accessed through a scheme employing entirely separate index and data ports. I/O address 3C0h (or memory address 3C0h) is used both as the read and write for the index register, and as the write address for the data port. I/O address 3C1h (or memory address 3C1h) is the read address for the data port.

To write to one of the attribute controller registers, the index of the desired register must be written to I/O address 3C0h (or memory address 3C0h), and then the data is written to the very same I/O (memory) address. A flip-flop alternates with each write to I/O address 3C0h (or memory address 3C0h) to change its function from writing the index to writing the actual data, and back again. This flip-flop may be deliberately set so that I/O address 3C0h (or memory address 3C0h) is set to write to the index (which provides a way to set it to a known state) by performing a read operation from Input Status Register 1 (ST01) at I/O address 3BAh (or memory address 3BAh) or 3DAh (or memory address 3DAh), depending on whether the graphics system has been set to emulate an MDA or a CGA as per MSR[0].

To read from one of the attribute controller registers, the index of the desired register must be written to I/O address 3C0h (or memory address 3C0h), and then the data is read from I/O address 3C1h (or memory address 3C1h). A read operation from I/O address 3C1h (or memory address 3C1h) does not reset the flip-flop to writing to the index. Only a write to 3C0h (or memory address 3C0h) or a read from 3BAh or 3DAh (or memory address 3BAh or 3DAh), as described above, will toggle the flip-flop back to writing to the index.

9.4.1.ARXAttribute Controller Index Register

I/O (and Memory Offset) Address:					3C0h
Default:					00UU UUUUb (U=Undefined)
Attributes:					Read/Write
7			6	5	4	0
		Reserved (00)		Video	Attribute Controller Register Index
				Enable
		Bit			Description
	7:6		Reserved. Read as 0s.
	5		Video Enable. Note that In the VGA standard, this is called the “Palette Address Source” bit.
			0 = Disable. Attribute controller color registers (AR[00:0F]) can be accessed by the processor.
			1 = Enable. Attribute controller color registers (AR[00:0F]) are inaccessible by the processor.
	4:0		Attribute Controller Register Index. These five bits are used to select any one of the attribute
			controller registers (AR[00:14]), to be accessed.
			Note:
			AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words “plane,” “color
			plane,” “display memory plane,” and “memory map” have been all been used in IBM* literature on the
			VGA standard to describe the four separate regions in the frame buffer where the pixel color or attribute
			information is split up and stored in standard VGA planar modes. This use of multiple terms for the
			same subject was deemed to be confusing, therefore, AR12 is called the Memory Plane Enable
			Register. Attribute Controller Register Index.

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