Intel 815 Display And Cursor Registers, DISPSL-Display Scan Line Count, Line Counter for Display

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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20.Display And Cursor Registers

The following are cursor, display, and pixel pipe registers in address range 70000h–7FFFFh.

20.1.DISP_SL—Display Scan Line Count

Memory Offset Address:	70000h
Default:	0000h
Attributes:	Read only

This register enables the read back of the display vertical line counter. In interlaced display modes the line counter is initialized to the field and is incremented by two at each HSYNC.

The display line values are from CRTTG (the CRT timing generator) or the TV/FP timing generator, depending on whether the TV/FP timing generator is enabled and not in FP VESA VGA Mode (LCDTV_C[31]=1 AND LCDTV_C[28]=0) or not. The line counter changes at the leading edge of HSYNC, and can be safely read during display enable active time.

When in TV/FP centering mode, scan line 0 is the first active scan line of the TV/FP, not the first line of the centered active display.

15	12	11	0
	Reserved		Line Counter for Display [11:0]
Bit			Descriptions
15:12	Reserved.
11:0	Line Counter for Display [11:00].

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