Intel 815 manual Instruction Target 14h, Flip type 0 Synch flip, 1 Async flip, Dword Length 00h

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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11.2.8.GFXCMDPARSER _FRONT_BUFFER_INFO

The GFXCMDPARSER _FRONT_BUFFER_INFO instruction is used to initialize the base address of the scene to be display by the Display Engine (DE) (a.k.a. flip). There are two choices for this instruction. In the first choice, the Instruction Parser sends the base address to the DE where its update is synchronized to the display syncs (sync flip). In the second choice, the DE’s update is on the following hsync (async flip).

In the case of a double buffer swap operation requiring a flip between the display and render surface base addresses, in addition to the FRONT_BUFFER_INFO packet a DEST_BUFFER_INFO instruction will also need to be specified. Note that no special hardware is provided to synchronize these instructions together.

A bit of the Interrupt Status Register represents the status of the flip instruction. This flag is set when the Instruction Parser processes the GFXCMDPARSER_FRONT_BUFFER_INFO instruction. For the sync flip, the flag is cleared when the vertical sync occurs. For async flip the flag is cleared when the hardware determines all the information for the new buffer is acquired, this is estimated to be 32 scan lines.

Setting and clearing this flag generates a system memory write to the location stored in the Hardware Status Vector Address Register, if unmasked in the Hardware Status Mask Register. Clearing this flag will generate an external interrupt, if unmasked in the Interrupt Mask Register and enabled in the Interrupt Enable Register.

The flush instruction should be issued prior to the flip instruction; this is to ensure that hardware pipeline and cache structures are flushed and the rendered scene that is to be displayed next is in memory. The flush instruction waits for the blitter and the render/map pipeline to be Not Busy and the local cache to be coherent with memory before parsing continues. The format of the GFXCMDPARSER_FRONT_BUFFER_INFO instruction is:

DWord	Bits	Description
0	31:29	Client: 000 – Instruction Parser
	28:23	Instruction Target: 14h
	22:20	Reserved. MBZ
	19:8	Front Buffer Pitch: A 12-bit value that specifies the number of QWs of frame buffer
		memory occupied by each horizontal row of characters. This loading is similar to the
		loading of the offset registers CR41(3:0):: CR13(7:0), except that the pitch in this case
		is specified in QWs. Will not be loaded in case of Async flip.
		Example of pitch computation for 1024x768 @ 16 bpp:
		1024 pixels * (2 B / 1 pixel) * (1 QW / 8 B) * (1 tile / 16 QW) = 16 tiles
	7	Reserved. MBZ
	6	Flip type: “0”: Synch flip, “1”: Async flip
	5:0	Dword Length: 00h
1	31:26	Reserved. MBZ
	25:3	Front Buffer Base Address: Virtual memory address bits 25:3 (max 64MB). The
		default value is 0. (unsigned int)
	2:0	Reserved. MBZ

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