Intel 815 manual DACMASKPixel Data Mask Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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used to choose the color data position that is to be written to through the same data port. This arrangement allows the same data port to be used for reading from and writing to two different color data positions. Reading and writing the color data at a color data position involves three successive reads or writes since the color data stored at each color data position consists of three bytes.

To read a color data position, the index of the desired color data position must first be written to the Palette Read Index Register. Then all three bytes of data in a given color data position may be read at the Palette Data Register. The first byte read from the Palette Data Register retrieves the 8-bit value specifying the intensity of the red color component, while the second and third bytes read are the corresponding 8-bit values for the green and blue color components, respectively. After completing the third read operation, the Palette Read Index Register is automatically incremented so that the data of the next color data position becomes accessible for being read. This allows the contents of all 256 color data positions of the palette to be read by specifying only the index of the 0th color data position in the Palette Read Index Register, and then simply performing 768 successive reads from the Palette Data Register.

Writing a color data position entails a very similar procedure. The index of the desired color data position must first be written to the Palette Write Index Register. Then all three bytes of data to specify a given color may be written to the Palette Data Register. The first byte written to the Palette Data Register specifies the intensity of the red color component, the second byte specifies the intensity for the green color component, and the third byte specifies the same for the blue color component. One important detail is that all three of these bytes must be written before the hardware will actually update these three values in the given color data position. When all three bytes have been written, the Palette Write Index Register is automatically incremented so that the data of the next color data position becomes accessible for being written. This allows the contents of all 256 color data positions of the palette to be written by specifying only the index of the 0th color data position in the Palette Write Index Register, and then simply performing 768 successive writes to the Palette Data Register.

In addition to the standard set of 256 color data positions of the palette, there is also an alternate set of 8 color data positions used to specify the colors used to draw the cursor, and these are also accessed using the very same sub-addressing scheme. A bit in the Pixel Pipeline Configuration Register (PIXCONF) determines whether the standard 256 color data positions or the alternate eight color data positions are to be accessed through this sub-addressing scheme.

9.5.1.DACMASKPixel Data Mask Register

I/O (and Memory Offset) Address: 3C6h

Default:Undefined

Attributes:Read/Write

Bit	Description
7:0	Pixel Data Mask. In indexed-color mode, the 8 bits of this register are logically ANDed with the 8 bits of
	pixel data received from the frame buffer for each pixel. The result of this ANDing process becomes the
	actual index used to select color data positions within the palette. This has the effect of limiting the
	choice of color data positions that may be specified by the incoming 8-bit data.
	0 = Corresponding bit in the resulting 8-bit index being forced to 0.
	1 = Allows the corresponding bit in the resulting index to reflect the actual value of the corresponding
	bit in the incoming 8-bit pixel data.
	In direct-color mode, the palette is not used, and the data in this register is ignored.

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