Intel 815 manual VSYNC-Vertical Sync Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

17.6.VSYNC—Vertical Sync Register

Address Offset:					60014h
Default Value:					00000000h
Access:					Read/Write
Size:					32 bits
31			28	27	16
			Reserved		Vertical Sync End
15			12	11	0
			Reserved		Vertical Sync Start
		Bit			Description
	31:28		Reserved.
	27:16		Vertical Sync End. Vertical sync end expressed in terms of absolute line numbers relative to the
			vertical active display start.
			Notes:
			1. When VSYNC Start is programmed equal to VBLNK Start, both VSYNC and VBLANK will be
			asserted on the same pixel clock.
			2. VSYNC Start programmed beyond the VTOTAL end will prevent the VSYNC start and VSYNC end
			to occur..
	15:12		Reserved.
	11:0		Vertical Sync Start. Vertical sync start expressed in terms of absolute line number relative to the
			vertical active display start.
			Notes:
			1. Minimum VSYNC width is 2 lines. A VSYNC programmed to 1 scan line does not generate the
			correct picture.
			2. An asserted VSYNC will be cleared as soon as VTOTAL end is reached, regardless of the value in
			the VSYNC End register.

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