Gfxrenderstatemaplodlimits, Opcode 3h | Intel 815 guide

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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13.9.GFXRENDERSTATE_MAP_LOD_LIMITS

The limits of the Level of Detail calculation can be controlled within GC for each Map. These values are specified in the following instruction as follows.

Figure 36. State Variable Relationships

Coordinate Sets

Map Information

Texels

Blending Stages

DWord	Bit	Description

0	31:29	Client : 03h – Rendering Engine

	28:24	3DState16 : 1Ch

	23:19	Opcode : 3h

	18:17	Reserved: 00h (Additional Maps)

	16	Update Map Index : The valid range is 0–1.

	15:14	Reserved: 00h

	13	Maximum Mip Level Mask : 0 = Do not update; 1 = Update

	12:5	Maximum Mip Level : This is an unsigned 4.4 bit value which defines the highest
		resolution map which may be accessed. A value of 0 equates to no limit on the mip
		map selection. Values 1 through 10 will force the mip map selection to be between the
		specified value and the highest defined mip map (the lowest resolution map). This
		value must be less than the Minimum Mip Level.

	4	Minimum Mip Level Mask : 0 = Do not update; 1 = Update

	3:0	Minimum Mip Level : This is an unsigned 4 bit value which defines the lowest
		resolution map which may be accessed. Values 0 through 10 will force the mip map
		selection to be between the maximum resolution mip map and the specified value.
		This value must be correctly identified for the current map (no assumptions are made
		about the number of mips associated with a particular map). This value must also be
		greater than the Maximum Mip Level.

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Intel 815 manual Gfxrenderstatemaplodlimits, Opcode 3h

Contents

Intel 815 Chipset Graphics Controller Programmer’s Reference Manual PRM Intel 815 Chipset Graphics Controller PRM, Rev Contents 100 106 141 Monosrccopyimmediateblt Gfxrenderstatemaplodlimits 15.4.3.3 HORZPH-Horizontal Phase Register 279 15.4.3.4 16.2.5 Figures Tables Date Revision HistoryRev This page is intentionally left blank Term Description IntroductionTerminology Reference Documents MCH Intel 815 Chipset Overview I/O Controller Hub Intel 82815 Chipset Gmch Overview Intel 82815 Chipset Gmch Block Diagram Host Interface Multiplexed AGP and Display Cache Interface Data Rate Signaling LevelSystem Memory Interface Hub Interface Intel 82815 Chipset Gmch Integrated Graphics Support Gmch Power Delivery Three PCI Devices on GmchSystem Clocking Front Side Bus System Memory Display Cache Interface Supported Single Monitor and Multi-monitor Configurations Multi-Mode Capability Requirements Configuration Single Monitor Multi-monitor Device Mode Auto-Detect Flowchart System Startup Software Start-Up Sequence Graphics Driver Startup Switching Device modes System Address Map System Memory Space Memory and I/O Space Registers Graphics Controller Register Memory and I/O Map Reserved 50000h−5FFFFh. Reserved in the Intel 815 chipset Address Offset Symbol Register Name Access GC Register Memory Address MapVGA and VGA Extended Registers Instruction and Interrupt Control Registers 01000h −02FFFh Instpm OV0ADD Ssladd VGA and Extended VGA Register Map Display and Cursor Control Registers 70000h-7FFFFh VGA and Extended VGA I/O and Memory Register Map Address Register Name Read Register Name Write 2D Registers Index Sym Register Name Indirect VGA and Extended VGA Register IndicesIndex Sym Description 2D Attribute Controller Registers 3C0h / 3C1h CR0F Graphics Address Translation Memory Buffers for GC’s Instruction Interface GTT Graphics Translation Table GTT Range Definition This page is intentionally left blank Basic Initialization Procedures Vendor Id Device Id PCI Device CharacteristicsInitialization Sequence Hardware Detection Probe Frame Buffer Initialization Hardware Register Initialization Hardware StateColor vs. Monochrome Monitors Protect Registers Locking and Unlocking Saving the Hardware State Restoring the Hardware State Intel 815 Chipset Graphics Controller PRM, Rev Intel 815 Chipset Graphics Controller PRM, Rev This page is intentionally left blank BLT Engine Programming Considerations When the Source and Destination Locations OverlapBlt Engine Programming Source Bblt3.vsd Destination Source Bblt4.vsd Basic Graphics Data Considerations Contiguous vs. Discontinuous Graphics Data Source Data Monochrome Source Data Pattern Data Pattern Data -- Always an 8x8 Array of Pixels Bpp Pattern Data -- Occupies 64 Bytes 8 quadwords Destination Data BLT Programming Examples Pattern Fill -- a Very Simple BLT Pattern Data for Example Pattern Fill BLT Results of Example Pattern Fill BLT Drawing Characters Using a Font Stored in System Memory On-Screen Destination for Example Character Drawing BLT Intel 815 Chipset Graphics Controller PRM, Rev Results of Example Character Drawing BLT Initialization Registers Standard VGA RegistersSmram Registers SMRAM-System Management RAM Control Register Device Bit Description RAM Initialization and Usage of Stolen Memory Display and Cursor Control Registers Clock Control and Power Management RegistersLCD/TV-Out Graphics Controller Registers 3CEh / 3CFh CRT Controller Registers 3B4h/3D4h/3B5h/3D5h Initialization Values for VGA Registers MSR GR01 00h This page is intentionally left blank Frame Buffer Access Intel 815 Chipset Graphics Controller PRM, Rev VGA and Extended VGA Registers General Control & Status RegistersName Function Read Write Memory Offset 1. ST00Input Status Bit Display Enable Output ST01Input StatusBit Descriptions Vertical Retrace/Video FCRFeature Control Reserved. Read as Vsync Control CRT HSync Polarity MSRMiscellaneous OutputCRT VSync Polarity Sequencer Registers SRXSequencer Index 2. SR00Sequencer Reset 3. SR01Clocking Mode Shift 4. SR02Plane/Map Mask Bit 10,4 Map Number Table Location 5. SR03Character FontBit 32 Map Number Table Location 6. SR04Memory Mode Register Made according to the value of the Plane Mask Register SR02 7. SR07Horizontal Character Counter Reset Graphics Controller RegistersGRXGRX Graphics Controller Index Register Bit Description Horizontal Character Counter 2. GR00Set/Reset Register 3. GR01Enable Set/Reset Register 4. GR02Color Compare Register 5. GR03Data Rotate Register 7. GR05Graphics Mode Register 6. GR04Read Plane Select Register Bits 65=1x Bits 65=00Bits 65=01 Write Mode Odd/Even ModeRead Mode Bit Graphics/Text Mode8. GR06Miscellaneous Register Bit Mask 9. GR07Color Don’t Care Register10. GR08Bit Mask Register Reserved To Local Memory Enable Packed Mode Enable11. GR10Address Mapping VGA Buffer/Memory Map Select 12. GR11Page Selector Supported Memory Offset Address 3CFh Index=14h-1fh Default Attribute 13. GR141FSoftware Flags Attribute Controller Registers ARXAttribute Controller Index Register 2. AR000FPalette Registers 0F 3. AR10Mode Control RegisterPalette Bits P5, P4 Select Pixel Width/Clock Select Enable Blinking/Select Background Intensity Enable Line Graphics Character CodeGraphics/Alphanumeric Mode Pixel Panning Compatibility Bit 54 ST01 Bit 5. AR12Memory Plane Enable Register4. AR11Overscan Color Register 6. AR13Horizontal Pixel Panning Register ReservedPixel Text Color Pixel Text Graphics VGA Color Palette Registers 7. AR14Color Select Register DACMASKPixel Data Mask Register DACSTATEDAC State Register DACRXPalette Read Index RegisterDACWXPalette Write Index Register Bits Index Register Indicated CRT Controller Register DACDATAPalette Data Register Display Fields and Dimensions CRxx Control Registers CRXCRT Controller Index Register 4. CR02Horizontal Blanking Start Register 3. CR01Horizontal Display Enable End Register2. CR00Horizontal Total Register 6. CR04Horizontal Sync Start Register Bit Amount of Delay5. CR03Horizontal Blanking End Register 7. CR05Horizontal Sync End Register 8. CR06Vertical Total Register 9. CR07Overflow Register 115 116 10. CR08Preset Row Scan Register Double Scanning Enable 11. CR09Maximum Scan Line Register 12. CR0AText Cursor Start Register 13. CR0BText Cursor End Register 14. CR0CStart Address High Register 15. CR0DStart Address Low Register 16. CR0EText Cursor Location High Register 17. CR0FText Cursor Location Low Register 18. CR10Vertical Sync Start Register 19. CR11Vertical Sync End Register 20. CR12Vertical Display Enable End Register CR13Offset Register CR146 CR176 Addressing Mode 22. CR14Underline Location RegisterCount By CR145 CR173 Address Incrementing Interval 23. CR15Vertical Blanking Start Register 24. CR16Vertical Blanking End Register CR146 CR176 25. CR17CRT Mode ControlWord Mode or Byte Mode Compatibility Mode Support Select Row Scan Counter DWord Mode Memory Address Counter Address Bits Frame Buffer Address Decoder CR17 bit 1=1 CR17 bit 1=0 CR17 bit 0=1 CR17 bit 0=0 26. CR18Line Compare Register 27. CR22Memory Read Latch Data Register 29. CR30Extended Vertical Total Register 30. CR31Extended Vertical Display End Register 31. CR32Extended Vertical Sync Start Register 32. CR33Extended Vertical Blanking Start Register Extended Horizontal Total MSB that extends CR00 33. CR35 Extended Horizontal Total Time Register34. CR39Extended Horizontal Blank Time Register 35. CR40Extended Start Address Register 36. CR41Extended Offset Register 37. CR42Extended Start Address High Register 39. CR80I/O Control Interlace Enable38. CR70Interlace Control Register 40. CR81Reserved 41. CR82Blink Rate Control Overview Programming InterfaceReserved Bits and Software Compatibility GC Register Programming GC Instruction StreamsInstruction Use Instruction Transport Overview Instruction Parser Interrupt Ring Ring Buffers RB Ring Buffer Registers Ring Buffer Use Characteristic DescriptionRing Buffer Initialization Batch Buffers Batch Buffer Sequence Wait Instructions Instruction ArbitrationArbitration Rationale Instruction Arbitration Rules Batch Buffer Protected ModeInstruction Arbitration Points Instructions Instruction FormatInstruction Parser Instructions Bits 3129 2824 210 Graphics Controller Instructions Client Instruction Client Instruction Parser Instructions IntroductionInstruction Descriptions DWord Bit Description Reserved MBZ Opcode 01hOpcode 02h Gfxcmdparserwaitforevent DWord Bit DWord Bits Description Dwordlength 00h Opcode 15hReserved 00000h Dword Length 00h Instruction Target 14hFlip type 0 Synch flip, 1 Async flip Opcode 16h Opcode 07h Opcode 08h Arbitration ON/OFFInstruction Target 11h Instruction Target 12h Word Bits Description Gfxcmdparserbatchbuffer Instruction Target 30h BLT Engine Instructions InstructionsBLTs To and From Cacheable Memory Setupblt Setup Background Color All Setup Foreground Color SLB & TB onlyInstruction Target Opcode 00h Dword Length 06h Instruction Target Opcode 10h Dword Length 07hColor Depth Raster Operation Pixelblt Instruction Target Opcode 20hInstruction Target Opcode 21h Destination X2 Coordinate Ending Right Dword Length 04h TextbltInstruction Target Opcode 22h TEXTImmediateBLT Instruction Target Opcode 30hImmediate Data DW Immediate Data DWs 2 through Dwordlength DWL Colorblt Instruction Target Opcode 40hDword Length 03h Solid Pattern Color Patblt Instruction Target Opcode 41h Mono Pattern Transparency Mode 1 = transparency enabled MonopatbltInstruction Target Opcode 42h Pattern Background Color Srccopyblt Instruction Target Opcode 43h Instruction Target Opcode 44h Line Source Background Color Source Foreground Color Mono Source Transparency Mode 1 = transparency enabled Instruction Target Opcode 61h Instruction Target Opcode 45h Destination Transparency Mode See BR00 definitionFullblt Fullmonosrcblt Destination Transparency Color Instruction Target Opcode 46h Instruction Target Opcode 47h Dword Length 09h 181 Instruction Target Opcode 48h Dword Length 0Ah 183 BLT Engine Instruction Definitions 12.3.1. BR00-BLT Opcode and Control 185 SolPat Rsvd Mono 187 12.3.3. BR02-Clip Rectangle Y1 Address 12.3.4. BR03-Clip Rectangle Y2 Address 12.3.5. BR04-Clip Rectangle X1 3128 Reserved. Must be Zero 2716 12.3.6. BR05-Setup Expansion Background Color 12.3.7. BR06-Setup Expansion Foreground Color 12.3.8. BR07-Setup Color Pattern Address 12.3.9. BR08-Destination X1 12.3.10. BR09-Destination Address and Destination Y1 Address 12.3.11. BR10-Destination Y2 Address Source Pitch Offset or Monochrome Source Quadwords 12.3.13. BR12-Source Address 12.3.14. BR13-BLT Raster OP, Control, and Destination Pitch Increment/Decrement Select Source Select Mode Dynamic Color Depth 12.3.15. BR14-Destination Width & Height 12.3.16. BR15-Color Pattern Address 12.3.18. BR17-Pattern Expansion Foreground Color 3124 Reserved. Must be Zero 230 12.3.20. BR19-Source Expansion Foreground Color SSLADD-Source Scan Line Address DSLH-Destination Scan Line Height DSLRADD-Destination Scan Line Read Address 204 Rendering Engine Instructions GfxprimitiveAxis Aligned Rectangles Primitive Winding Order Primitive Rendering Instruction Format Position MaskBias Variable Length Vertex Formats for Rendering Instructions Vertex Attribute Comments Gfxvertex Gfxrenderstatevertexformat Gfxblock Rendering Block 1EhBlock Type Block Pattern Format Prediction Type DWord BitsVertical Motion Vector Precision 00 = 1/2 pixel 212 Precision Format Range Non-pipelined State VariablesMotion Vector Format Gfxrenderstatemaptexels Gfxrenderstatemapcoordsets Update Coordinate Set Index The valid range is Normalized Coordinate Set Mask 0 = Do not update 1 = UpdateOpcode 1h Normalized Coordinate Set Gfxrenderstatemapinfo Discrete Integrated Base Utilize Fence Tiled Surface Walk 3DstateMW 1Dh Dwordlength 2hReserved 0h Surface Format Color Space Conversion Enable 1511 221 Gfxrenderstatemapfilter Reserved 00h Mip Mode Filter Valid values are Opcode 2h Gfxrenderstatemaplodlimits Opcode 3h Opcode 4h Texture LOD Dither Weight Mask 0 = Do not update 1 = UpdateGfxrenderstatemaplodcontrol Opcode 82h Gfxrenderstatemappaletteload3DStateMWNPNon-pipelined 1Dh Gfxrenderstatemapcolorblendstages Blend Equation Description Update Blending Stage Index The valid range is 3DState24 00hWrite result to Current Register or Accumulator Select Replicate Arg1 Alpha to Color Channels Invert Color Arg2 Gfxrenderstatemapalphablendstages Invert Alpha Arg2 3DState24 01hInvert Alpha Arg1 Gfxrenderstatecolorfactor Instruction 1h Kill Pixel Mode Gfxrenderstatecolorchromakey KeyedPixelControl KeyedPixelControl Write Mask 0 = Do not update 1 = UpdateInstruction 2h Monochrome Specular Full Color RGB GfxrenderstatesrcdstblendmonoNo Specular 236 Opcode Source / Destination Blend State 3DState24NP Non-pipelined 14h Alpha Reference State Mask 1 = Update 0 = Do Not UpdateGfxrenderstatezbiasalphafuncref Gfxrenderstatelinewidthcullshade Mode Alpha Shade Mode State Mask 1 = Update 0 = Do Not Update Specular Shade Mode State Mask 1 = Update 0 = Do Not UpdateColor Shade Mode State Mask 1 = Update 0 = Do Not Update 2824 3DState24 02h Alpha Setup Enable Enable Mask 1 = Update 0 = Do Not Update Color Index Key Enable Mask 1 = Update 0 = Do Not UpdateSpecular Enable State Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA1 Specular Dither Enable Mask 1 = Update 0 = Do Not Update Frame Buffer Write Enable Mask 1 = Update 0 = Do Not UpdateBuffer Write Enable Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA2 3DState24NP Non-pipelined 15h GfxrenderstatefogcolorGfxrenderstatedrawingrectangleinfo 3DStateMWNP Non-pipelined 1Dh Opcode 80h Gfxrenderstatescissorenable Scissor Rectangle Enable Mask 1 = Update 0 = Do Not Update3DState16NP Non-pipelined 1Ch Opcode 10h Gfxrenderstatescissorrectangleinfo Opcode 81h Stipple Pattern Stipple PatternOpcode 83h Gfxrenderstateantialiasing Gfxrenderstateprovokingvtxpixelization Rule Vertex Sequence Small Triangle Filter Enable Mask Pixelization Rule Mask Gfxrenderstatedestbuffervariables Opcode 85h Dest Buffer Format 0h = Any 8-bit Surface Programming Hints/Rules Drawing and Scissor Rectangles Color Calculator 255 256 Clock Control Registers Programming Notes DCLK0D-Display Clock 0 Divisor Register Example Programming Sequence DCLK2 DCLK1D-Display Clock 1 Divisor Register DCLK2D-Display Clock 2 Divisor Register LCDCLKD-LCD Clock Divisor Register Reserved VCO Loop Divide LCD Clock DCLK0DS-Display & LCD Clock Divisor Select RegisterPost Divisor Select LCD Clock Post Divisor Select clock VCO Loop Divide clock PWRCLKC-Power Management and Miscellaneous Clock Control Internal DAC Enable Overlay Registers Register/Instruction Category Comment 15.1. OV0ADD-Overlay 0 Register Update Address Register Updating Register Values DOV0STA-Display/Overlay 0 Status Register Gamma Correction GAMC50-Gamma Correction Registers Red Green Blue Mathematical Gamma Correction For Overlay Three times Gamma Correction Theory Of Operation Latch Address Gamma Hardware Implementation Memory Offset Registers Overlay Buffer Pointer RegistersOBUF0Y-Overlay Buffer 0 Y Pointer Register Format Alignment OBUF1Y-Overlay Buffer 1 Y Pointer Register OBUF0U-Overlay Buffer 0 U Pointer Register Bit Descriptiont OBUF0V-Overlay Buffer 0 V Pointer RegisterOBUF1U-Overlay Buffer 1 U Pointer Register 15.4.2.1. OV0STRIDE-Overlay 0 Stride Register Overlay Stride RegistersOBUF1V-Overlay Buffer 1 V Pointer Register Overlay Initial Phase Registers YRGBVPH-Y/RGB Vertical Phase Register UVVPH-UV Vertical Phase Register HORZPH-Horizontal Phase Register INITPH-Initial Phase Register DWINSZ-Destination Window Size Register Overlay Destination Window Position/Size RegistersDWINPOS-Destination Window Position Register Overlay Source Size Registers SWID-Source Width Register SWIDQW-Source Width In QWords Register SHEIGHT-Source Height Register Overlay Scale Factor Registers YRGBSCALE-Y/RGB Scale Factor Register UVSCALE-UV Scale Factor Register 15.4.7.2. OV0CLRC1-Overlay 0 Color Correction 1 Register Overlay Color Correction Registers15.4.7.1. OV0CLRC0-Overlay 0 Color Correction 0 Register Overlay Destination Color Key Registers DCLRKV-Destination Color Key Value Register DCLRKM-Destination Color Key Mask Register Destination Constant Alpha Blend EnableAlways Constant Alpha Blend Enable Overlay Source Color Key Registers SCLRKVH-Source Color Key Value High Register SCLRKVL-Source Color Key Value Low Register SCLRKM-Source Color Key Mask Register Source Constant Alpha Blend Enable Overlay Configuration Registers 15.4.10.1. OV0CONF-Overlay Configuration Register 15.4.11. OV0CMD-Overlay Command Register Vertical Chrominance Filter. Vertical Chrominance Filter Vertical Luminance Filter. Vertical Luminance Filter Automatic flipping Manual flip commandSource Format 297 Overlay Alpha Blend Window Position/Size Registers AWINPOS-Alpha Blend Window Position Register Overlay Flip Instruction AWINSZ-Alpha Blend Window Size Register 300 FENCE-Graphics Memory Fence Table Registers Instruction, Memory, and Interrupt Control RegistersInstruction Control Registers Reserved for address bits 31 downto Tile walkFence size Fence Pitch PGTBLCTL-Page Table Control Register Normal Invalidation Mechanism PGTBLER-Page Table Error Register Error Type PGTBLERRMSK-Page Table Error Mask Register Buffer Unit Page Table Error Mask Command Streamer DMA Page Table Error MaskOverlay Page Table Error Mask Display Page Table Error Mask RINGBUF-Ring Buffer Registers Intel 810 Chipset and Intel815 Chipset Errata Reserved Ring Buffer Valid HWSPGA-Hardware Status Page Address Register DWord Description Offset IPEIR-Instruction Parser Error Identification Register debug IPEHR-Instruction Parser Error Header Register debug This read only register reports engine done signals INSTDONE-Instruction Stream Interface Done Register NOPID-NOP Identification Register INSTPM-Instruction Parser Mode Register Disable State Variable Updates INSTPS-Instruction Parser State Register debug Cscpr State Machine Command Parser BBPPTR-Batch Buffer Parser Pointer Register debug ABBSTR-Active Batch Buffer Start Address Register debug Current DMA Address Reserved User of the DMA Engine ABBEND-Active Batch Buffer End Address Register debugDMAFADD-DMA Engine Fetch Address debug MEMMODE-Memory Interface Mode Register debug Reserved Host Graphics Prefetch ModeGraphics Address Translation Mode Instruction Fifo Debug Mode Interrupt Control Registers Bit Definition For Interrupt Control Registers 321 HWSTAM-Hardware Status Mask Register IER-Interrupt Enable Register Interrupt Enables. See Table IIR-Interrupt Identity Register Interrupt Identity. See. Table IMR-Interrupt Mask Register Interrupt Mask Bits. See. Table ISR-Interrupt Status Register Error Identity, Mask and Status Registers Table Error handling in Intel 815 Chipset Resetting the Page Table Error Table Error EIR-Error Identity Register EMR-Error Mask Register ESR-Error Status Register Display Interface Control FWBLC-FIFO Watermark and Burst Length Control 332 LCD / TV-Out Register Description HTOTAL-Horizontal Total Register HBLANK-Horizontal Blank Register HSYNC-Horizontal Sync Register VTOTAL-Vertical Total Register VBLANK-Vertical Blank Register VSYNC-Vertical Sync Register Sync Polarity Control LCD / TV-Out EnableLCDTVC-LCD/TV-Out Control Register FP Vesa VGA Mode FP / 740 Data OrderingFpvsync Control Fphsync Control Border Enable Fphsync Output ControlActive Data Order Active Data Polarity OVRACT-Overlay Active Register BCLRPAT- Border Color Pattern Register Local Memory Interface DRT-DRAM Row Type Reserved Paging Mode Control PMC Bit RAS#-to-CAS# delay t RCDDRAMCL-DRAM Control Low Bit RAS# act. To precharge t RAS Refresh to RAS# act. t RC DRAMCH-DRAM Control High 346 HSYNC/VSYNC Control1916 19. I/O Control RegistersHVSYNC-HSYNC/VSYNC Control Register Gpio Registers GPIOAGeneral Purpose I/O Control Register a Value .bit GPIOBGeneral Purpose I/O Control Register B 351 352 Line Counter for Display Display And Cursor RegistersDISPSL-Display Scan Line Count DISPSLC-Display Scan Line Count Range Compare Inclusive / Exclusive PIXCONF-Pixel Pipeline Configuration Reserved Display path Graphics Gamma Enable. See noteOverlay path Gamma Enable. See note Pixel Pipeline Control Display Color Mode Bit DAC EnableEnable Extended Status Read Mode CRT Overscan Color GUI Mode Transition from VGA modes to hires mode or oppositeBLTCNTL-BLT Control SWF13-Software Flag Registers DPLYBASE-Display Base Address Register Reserved Flat Panel Hot Plug Detect Enable Vertical Sync Status EnableDisplay Line Compare Enable DPLYSTAS-Display Status Select Register Vertical Blank Enable Overlay Registers Upated EnableOverlay Registers Updated Status Vertical Sync Status Reserved Cursor Coordinate System Origin Select Hardware CursorCURCNTR-Cursor Control Register CURBASE-Cursor Base Address Register CURPOS-Cursor Position Register Appendix a Mode Parameters Parameters for Screen Resolution/Refresh Rate 320x20070Hz = Parameters for Screen Resolution/Refresh Rate 320x24070Hz = Parameters for Screen Resolution/Refresh Rate 352X48070Hz = Parameters for Screen Resolution/Refresh Rate 352X57670Hz = Parameters for Screen Resolution/Refresh Rate 400x30070Hz = Parameters for Screen Resolution/Refresh Rate 512X38470Hz = Parameters for Screen Resolution/Refresh Rate 640x35085Hz = Parameters for Screen Resolution/Refresh Rate 640x40070Hz = Parameters for Screen Resolution/Refresh Rate 640x40085Hz = Parameters for Screen Resolution/Refresh Rate 640x48060Hz = Parameters for Screen Resolution/Refresh Rate 640x48070Hz = Parameters for Screen Resolution/Refresh Rate 640x48072Hz = Parameters for Screen Resolution/Refresh Rate 640x48075Hz = Parameters for Screen Resolution/Refresh Rate 640x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x40085Hz = Parameters for Screen Resolution/Refresh Rate 720x48060Hz = Parameters for Screen Resolution/Refresh Rate 720x48075Hz = Parameters for Screen Resolution/Refresh Rate 720x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x57660Hz = Parameters for Screen Resolution/Refresh Rate 720x57675Hz = Parameters for Screen Resolution/Refresh Rate 720x57685Hz = Parameters for Screen Resolution/Refresh Rate 800x60056Hz = Parameters for Screen Resolution/Refresh Rate 800x60060Hz = Parameters for Screen Resolution/Refresh Rate 800x60070Hz = Parameters for Screen Resolution/Refresh Rate 800x60072Hz = Parameters for Screen Resolution/Refresh Rate 800x60075Hz = Parameters for Screen Resolution/Refresh Rate 800x60085Hz = Parameters for Screen Resolution/Refresh Rate 854X48060Hz = Parameters for Screen Resolution/Refresh Rate 854X48075Hz = Parameters for Screen Resolution/Refresh Rate 854X48085Hz = 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 Intel around the world