Intel 815 manual INSTPS-Instruction Parser State Register debug

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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16.1.12. INSTPS—Instruction Parser State Register (debug)

Address Offset:	020C4h
Default Value:	0000h
Access:	Read Only
Size:	32 bits

This register contains the state code of the Instruction Parser in the CSI. Decoding the contents of this register will indicate what the Instruction Parser is currently doing.

31							17	16
				Reserved				CSINTR
15		14	13	12	11	10	9	8
CSINTR		CSSTDW		Reserved	CSDMA		CSSW
(cont.)
7				4	3			0
		CSARB				CSCPR
Bit					Description
31:17	Reserved
16:15	CSINTR State Machine: Is responsible for the working the CS-PI Interrupt cycle generation interface.
	00 = INTRIDLE: This is the reset state. It is also the idle state. The state machine comes back to this
		state on getting acknolwedged in either of the two request states.
	01 = INTREQON: In this state the command stream turns on the interrupt flag to the HubLink unit and
		requests service
	11 = INTREQOFF: In this state the command stream turns off the interrupt flag to the HubLink unit and
		requests service
14:13	CSSTDW State Machine: Is responsible for generation of the Store DWord snoop cycle to the PI unit
	on behalf of the command parser and the interrupt report meachnism.
	000	= STDWIDLE: Waiting for next Store DWord Cycle
	001	= STDWINTR: INT Report Store DWord Cycle in progress
	010	= STDWCP: Command Parser Initiated Store DWord Cycle
	100	= STDWAUTO: Auto report of head pointer
	011	= STDWINTD: Request accepted, wait for HT to take data
	101	= STDWCPD: Request accepted, wait for HT to take data
	110	= STDWAUTD: Request accepted, wait for HT to take data
12	Reserved

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