Intel 815 manual Srccopyblt, Instruction Target Opcode 43h

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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12.2.10. SRC_COPY_BLT

This BLT instruction performs a color source copy where the only operands involved is a color source and destination of the same bit width.

The source and destination operands may overlap, which means that the X and Y directions can be either forwards or backwards. The X direction field applies to both the destination and source operands. The source and destination pitches can be either sign.

Requirements:

•The Intel® 815 chipset hardware has a restriction that the BLT color source and destination operands must not co-exist on the same 32-Byte cacheline. To work-around this issue :

For BLTs that have sharing of a cacheline for a given scanline, the driver must treat this as an overlapping BLT case.

For linear memory, the surfaces allocated must be 32B-cacheline aligned.

•Three instructions are affected by this hardware restriction : SRC_COPY_BLT, FULL_BLT, and FULL_MONO_PATTERN_BLT. Essentially any instruction with Color Source & Destination will have the above restriction.

DWord	Bit	Description
0 = BR00	31:29	Client : 02h – 2D Processor
	28:22	Instruction Target (Opcode) : 43h
	21:05	Reserved. Must be Zero
	04:00	Dword Length : 04h
1 = BR13	31	Reserved. Must be Zero
	30	X Direction (1 = written from right to left (decrementing = backwards); 0 =
		incrementing)
	29:28	Reserved. Must be Zero
	27	Reserved. Must be Zero
	26	Must Be One (‘1’).
	25:24	Color Depth:
		00 = 8 bit color
		01 = 16 bit color
		10 = 24 bit color
		11 = reserved
	23:16	Raster Operation:
	15:00	Destination Pitch (signed): (13:00 are implemented in Intel® 810 chipset)
2 = BR14	31:16	Destination Height (in scan lines): (28:16 are implemented in Intel® 810 chipset)
	15:00	Destination Width (in bytes): (12:00 are implemented in Intel® 810 chipset)
3 = BR09	31:00	Destination Address: Address of the first byte to be written
		(25:00 are implemented in Intel® 810 chipset)
	31:14	Reserved. Must be Zero
4 = BR11	13:00	Source Pitch (quadword aligned and signed): (13:00 are implemented in Intel®
		810 chipset)
5 = BR12	31:00	Source Address: (25:00 are implemented in Intel® 810 chipset)

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