Intel 815 manual Word Bits Description

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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11.2.14. GFXCMDPARSER_LOAD_SCAN_LINES_EXCL

This instruction is used to initialize the scan line window registers in the Display engine. If the display refresh is outside this window, the display engine asserts a signal that is used by the instruction parser to process the WAIT_FOR_EVENT instruction. This instruction overrides any previous INCL instruction. The format is:

Word	Bits	Description
0	31:29	Client: 000 – Instruction Parser
	28:23	Instruction Target: 13h
	22:6	Reserved.
	5:0	DWord Length: 00h
1	31:16	Start Scan Line Number. (Line 0 is the first line of the display frame)
	15:0	End Scan Line Number. (Line 0 is the first line of the display frame)

11.2.15. GFXCMDPARSER_STORE_DWORD_IMM

This instruction immediately causes a system write of the data word in the packet to the address which is also in the instruction packet. Note: All store DWords will invalidate the host - graphics pre-fetch cache. The GFXCMDPARSER_STORE_DWORD_IMM instruction format is:

DWord	Bit	Description
0	31:29	Client: 000 – Instruction Parser
	28:23	Instruction Target: 20h
	22:6	Reserved.
	5:0	DWord Length: 01h
1	31:2	Address: DWord aligned. The hardware only uses bits 31:2.
	1:0	Reserved. MBZ
2	31:0	Data Word

11.2.16. GFXCMDPARSER_STORE_DWORD_INDEX

This instruction immediately causes a system write of the data word in the packet to the address which is provided in the Hardware Status Page Address Register at offset specified.

Note: All store DWords will invalidate the host-graphics prefetch cache.

DWord	Bit	Description
0	31:29	Client: 000 – Instruction Parser
	28:23	Instruction Target: 21h
	22:6	Reserved: 0000h
	5:0	Dword Length: 01h
1	31:12	Reserved.
	11:2	Dword Offset into a page: A (11:2)
	1:0	Reserved.
2	31:0	Data Word

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