Intel 815 manual PGTBLCTL-Page Table Control Register, Normal Invalidation Mechanism

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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16.1.2.PGTBL_CTL—Page Table Control Register

Address Offset:	02020h
Default Value:	00000000h
Access:	Read/Write
Size:	32 bits

This register enables/disables the page table mechanism and when enabled, also sets the base address of the 4 KB aligned page table.

The driver will write this register when it creates the page table at the start of virtual mode. A 64 KB physical contiguous region in memory-mapped space will be re-mapped to the page table located in local memory. Driver writes to this memory-mapped space will be offset into the page table as defined by the page table base. The physical address will be the combination of the page table base and page table offset derived from the memory mapped driver write. A translation resource access (TLB access) with the page table disabled results in an interrupt. This interrupt only occurs if there is a write through the TLB (the page table can be disabled and the display and overlay still runs with no interrupt or error reporting).

The page table can be disabled when there is no drawing engine (render-map/blitter) or high priority stream (overlay/display) active. The hardware incorporates several TLBs that cache page table entries. Disabling the page table through this register will invalidate all TLBs except the one serving display and overlay. The following table lists all the TLBs and their invalidation mechanism.

	TLB		Normal Invalidation Mechanism			Note
Display			Refreshed on Vsync		Is not affected by bit 0
Overlay			Refreshed on Vsync		Is not affected by bit 0
Render/Blit			Flush		Is invalidated by page table disable
Host			Through a Page table write		Is invalidated by page table disable
Mapping			Through a Page table write		Is invalidated by page table disable
Command Stream			Through a Page table write		Is invalidated by page table disable
31				12		11	1		0
		Page Table Base Address				Reserved		Pg Tbl
			(4 KB aligned)					Enable
	Bit		Description
31:12		Page Table Base address 4 KB aligned. Has to be within Main Memory. This is a physical address
		(no GTT translation).
11:1		Reserved
0		Page Table Enable. If the graphics memory range is accessed through the graphics translation table
		when this bit is not set asserts an interrupt event. All graphics streams other than cursor and VGA fall
		under this category.
		0 = Disable
		1 = Enable

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