Intel 815 manual Color Space Conversion Enable, 1511

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

DWord

1

1

Bit Description

18Color Space Conversion Enable:

0 = Do not perform conversion.

1 = Perform color space conversion assuming biased chromanance values.

17Vertical Line Stride: The number of lines to skip between logically adjacent lines. The Forward/Backward Reference Picture Structure bits override this value when processing the GFXBLOCK instruction.

0 = Do not skip any lines.

1 = Skip 1 line. (provides support of Interleaved/field surfaces)

16Vertical Line Stride Offset: The number of lines to add as an initial offset when the Vertical Line Stride is 1. This value is overridden by the Forward/Backward Reference Picture Structure bits when processing the GFXBLOCK instruction.

0 = Add no offset. (top field)

1 = Add 1. (bottom field)

15:11 Reserved: 00h

10Utilize Fence Registers: If enabled the Tiled Surface, Tile Height, Tile Walk and Pitch are ignored. All request addresses are compared with the fence registers and the parameters associated with any matching fence register are utilized in the tiler. Otherwise, the specified Tile Walk is utilized.

0 = Disable Fence Register Utilization

1 = Enable Fence Register Utilization

9Tiled Surface: Specifies the whether the surface is organized as rectangular memory or as tiled memory. This field is ignored when the fence registers are being utilized.

0 = Linear (Rectangular memory)

1 = Tiled

8Tile Walk: The direction of increasing sequential addresses. This field is ignored when the fence registers are being utilized or the surface is linear.

0 = X-Major

1 = Y-Major

7:5 Reserved: 00h (For Tile Height)

4Reserved: 00h

3:0	Pitch: Log2 of the surface pitch is specified in quadwords. If the surface resides in a
	fenced region, this value must correspond to the pitch specified when programming
	the fence registers.

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