Intel 815 manual 19. CR11Vertical Sync End Register, Bit

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.6.19.CR11Vertical Sync End Register

I/O (and Memory Offset) Address:						3B5h/3D5h (index=11h)
Default:						0U00 UUUUb (U=Undefined)
Attributes:						Read/Write
7				6	5	4	3	0
		Protect		Reserved	Vert Int	Vert Int		Vertical Sync End
		Regs 0:7			Enable	Clear
		Bit					Description
	7		Protect Registers [0:7]. Note that the ability to write to Bit 4 of the Overflow Register (CR07) is not
			affected by this bit (i.e., bit 4 of the Overflow Register is always writeable).
			0 = Enable writes to registers CR[00:07]. (default)
			1 = Disable writes to registers CR[00:07].
	6		Reserved. In the VGA standard, this bit was used to switch between 3 and 5 frame buffer refresh cycles
			during the time required to draw each horizontal line.
	5		Vertical Interrupt Enable. Note that the graphics controller does not provide an interrupt signal which
			would be connected to an input of the system’s interrupt controller. Bit 7 of Input Status Register 0
			(ST00) indicates the status of the vertical retrace interrupt, and can be polled by software to determine if
			a vertical retrace interrupt has taken place. Bit 4 of this register can be used to clear a pending vertical
			retrace interrupt.
			0 = Enable the generation of an interrupt at the beginning of each vertical retrace period.
			1 = Disable the generation of an interrupt at the beginning of each vertical retrace period.
	4		Vertical Interrupt Clear. Note that the graphics controller does not provide an interrupt signal which
			would be connected to an input of the system’s interrupt controller. Bit 7 of Input Status Register 0
			(ST00) indicates the status of the vertical retrace interrupt, and can be polled by software to determine if
			a vertical retrace interrupt has taken place. Bit 5 of this register can be used to enable or disable the
			generation of vertical retrace interrupts.
			0 = Setting this bit to 0 clears a pending vertical retrace interrupt. This bit must be set back to 1 to
				enable the generation of another vertical retrace interrupt.
	3:0		Vertical Sync End. This 4-bit field provides a 4-bit value that specifies the end of the vertical sync pulse
			relative to its beginning. This 4-bit value should be set to the least significant 4 bits of the result of
			adding the length of the vertical sync pulse in terms of the number of scan lines that occur within the
			length of the vertical sync pulse to the value that specifies the beginning of the vertical sync pulse (see
			the description of the Vertical Sync Start Register for more details).

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