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Intel 815 manual OVRACT-Overlay Active Register, BCLRPAT- Border Color Pattern Register

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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

17.8.OVRACT—Overlay Active Register

Address Offset:					6001Ch
Default Value:					00000000h
Access:					Read/Write
Size:					32 bits
31				27	26	16
			Reserved		Overlay Active End

15			12	11		0
			Reserved		Overlay Active Start


		Bit			Description

	31:27		Reserved.
	26:16		Overlay Active End. This filed takes into account the Overlay pipeline delays for turning off the overlay
			at the end of a scan line. When LCD / TV is enabled, then the overlay active end is controlled by the
			LCD / TV-Out Timing Generator and uses all the bits. When LCD / TV is disabled, then the overlay
			active end is controlled by the VGA Timing Generator and uses bits 15:3 for character clock resolution.
	15:12		Reserved.
	11:0		Overlay Active Start. This field takes into account the Overlay pipeline delays for lining up X=0 to the
			first active pixel. When LCD / TV is enabled, then the overlay active start is controlled by the LCD /
			TV-Out Timing Generator and all the bits are used. When LCD / TV is disabled, then the overlay active
			start is controlled by the VGA Timing Generator and uses bits 15:3 for character clock.

17.9.BCLRPAT— Border Color Pattern Register

Address Offset:	60020h
Default Value:	00000000h
Access:	Read/Write
Size:	32 bits

A border is sent if Border Enable is on. Also same color will be sent during pseudo border period in LCD no-scalar mode.

In VGA Centering mode, the VGA border color will be sent instead of the Flat Panel Border Color. HIRes Centering mode will still use the Flat Panel Border color.

31		25	24	16	15		8	7	0
		Reserved	Red			Green			Blue


	Bit				Description

31:25		Reserved.
24:16		Red.
15:8		Green.
7:0		Blue.

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Intel 815 manual OVRACT-Overlay Active Register, BCLRPAT- Border Color Pattern Register

Contents

Intel 815 Chipset Graphics Controller Programmer’s Reference Manual PRMIntel 815 Chipset Graphics Controller PRM, Rev Contents 100 106 141 Monosrccopyimmediateblt Gfxrenderstatemaplodlimits 15.4.3.3 HORZPH-Horizontal Phase Register 279 15.4.3.4 16.2.5 Figures Tables Revision History RevDate This page is intentionally left blank Introduction TerminologyTerm Description Reference Documents MCHIntel 815 Chipset Overview I/O Controller Hub Intel 82815 Chipset Gmch OverviewIntel 82815 Chipset Gmch Block Diagram Host InterfaceData Rate Signaling Level System Memory InterfaceMultiplexed AGP and Display Cache Interface Hub Interface Intel 82815 Chipset Gmch Integrated Graphics SupportSystem Clocking Gmch Power DeliveryThree PCI Devices on Gmch Front Side Bus System Memory Display Cache InterfaceSupported Single Monitor and Multi-monitor Configurations Multi-Mode Capability RequirementsConfiguration Single Monitor Multi-monitor Device Mode Auto-Detect Flowchart System StartupSoftware Start-Up Sequence Graphics Driver Startup Switching Device modes System Address Map System Memory SpaceMemory and I/O Space Registers Graphics Controller Register Memory and I/O MapReserved 50000h−5FFFFh. Reserved in the Intel 815 chipset VGA and VGA Extended Registers Address Offset Symbol Register Name AccessGC Register Memory Address Map Instruction and Interrupt Control Registers 01000h −02FFFhInstpm OV0ADD Ssladd VGA and Extended VGA Register Map Display and Cursor Control Registers 70000h-7FFFFhVGA and Extended VGA I/O and Memory Register Map Address Register Name Read Register Name Write 2D RegistersIndirect VGA and Extended VGA Register Indices Index Sym DescriptionIndex Sym Register Name 2D Attribute Controller Registers 3C0h / 3C1h CR0F Graphics Address Translation Memory Buffers for GC’s Instruction Interface GTTGraphics Translation Table GTT Range Definition This page is intentionally left blank Initialization Sequence Basic Initialization ProceduresVendor Id Device Id PCI Device Characteristics Hardware Detection ProbeFrame Buffer Initialization Color vs. Monochrome Monitors Hardware Register InitializationHardware State Protect Registers Locking and UnlockingSaving the Hardware State Restoring the Hardware State Intel 815 Chipset Graphics Controller PRM, Rev Intel 815 Chipset Graphics Controller PRM, Rev This page is intentionally left blank When the Source and Destination Locations Overlap Blt Engine ProgrammingBLT Engine Programming Considerations Source Bblt3.vsd Destination Source Bblt4.vsd Basic Graphics Data Considerations Contiguous vs. Discontinuous Graphics DataSource Data Monochrome Source Data Pattern Data Pattern Data -- Always an 8x8 Array of PixelsBpp Pattern Data -- Occupies 64 Bytes 8 quadwords Destination Data BLT Programming Examples Pattern Fill -- a Very Simple BLTPattern Data for Example Pattern Fill BLT Results of Example Pattern Fill BLT Drawing Characters Using a Font Stored in System Memory On-Screen Destination for Example Character Drawing BLTIntel 815 Chipset Graphics Controller PRM, Rev Results of Example Character Drawing BLT Smram Registers Initialization RegistersStandard VGA Registers SMRAM-System Management RAM Control Register DeviceBit Description RAMInitialization and Usage of Stolen Memory Clock Control and Power Management Registers LCD/TV-OutDisplay and Cursor Control Registers Graphics Controller Registers 3CEh / 3CFh CRT Controller Registers 3B4h/3D4h/3B5h/3D5hInitialization Values for VGA Registers MSRGR01 00h This page is intentionally left blank Frame Buffer Access Intel 815 Chipset Graphics Controller PRM, Rev Name Function Read Write Memory VGA and Extended VGA RegistersGeneral Control & Status Registers Offset1. ST00Input Status BitBit Descriptions Display Enable OutputST01Input Status Vertical Retrace/VideoFCRFeature Control Reserved. Read as Vsync ControlMSRMiscellaneous Output CRT VSync PolarityCRT HSync Polarity Sequencer Registers SRXSequencer Index2. SR00Sequencer Reset 3. SR01Clocking Mode Shift4. SR02Plane/Map Mask 5. SR03Character Font Bit 32 Map Number Table LocationBit 10,4 Map Number Table Location 6. SR04Memory Mode Register Made according to the value of the Plane Mask Register SR02GRXGRX Graphics Controller Index Register 7. SR07Horizontal Character Counter ResetGraphics Controller Registers Bit Description Horizontal Character Counter2. GR00Set/Reset Register 3. GR01Enable Set/Reset Register4. GR02Color Compare Register 5. GR03Data Rotate Register7. GR05Graphics Mode Register 6. GR04Read Plane Select RegisterBits 65=00 Bits 65=01Bits 65=1x Odd/Even Mode Read ModeWrite Mode Graphics/Text Mode 8. GR06Miscellaneous RegisterBit 9. GR07Color Don’t Care Register 10. GR08Bit Mask RegisterBit Mask 11. GR10Address Mapping Reserved To Local Memory EnablePacked Mode Enable VGA Buffer/Memory Map Select12. GR11Page Selector SupportedMemory Offset Address 3CFh Index=14h-1fh Default Attribute 13. GR141FSoftware FlagsAttribute Controller Registers ARXAttribute Controller Index RegisterPalette Bits P5, P4 Select 2. AR000FPalette Registers 0F3. AR10Mode Control Register Pixel Width/Clock SelectGraphics/Alphanumeric Mode Enable Blinking/Select Background IntensityEnable Line Graphics Character Code Pixel Panning Compatibility5. AR12Memory Plane Enable Register 4. AR11Overscan Color RegisterBit 54 ST01 Bit Pixel Text Color 6. AR13Horizontal Pixel Panning RegisterReserved Pixel Text GraphicsVGA Color Palette Registers 7. AR14Color Select RegisterDACMASKPixel Data Mask Register DACWXPalette Write Index Register DACSTATEDAC State RegisterDACRXPalette Read Index Register Bits Index Register IndicatedCRT Controller Register DACDATAPalette Data RegisterDisplay Fields and Dimensions CRxx Control Registers CRXCRT Controller Index Register3. CR01Horizontal Display Enable End Register 2. CR00Horizontal Total Register4. CR02Horizontal Blanking Start Register Bit Amount of Delay 5. CR03Horizontal Blanking End Register6. CR04Horizontal Sync Start Register 7. CR05Horizontal Sync End Register 8. CR06Vertical Total Register 9. CR07Overflow Register115 116 10. CR08Preset Row Scan Register Double Scanning Enable 11. CR09Maximum Scan Line Register12. CR0AText Cursor Start Register 13. CR0BText Cursor End Register14. CR0CStart Address High Register 15. CR0DStart Address Low Register 16. CR0EText Cursor Location High Register17. CR0FText Cursor Location Low Register 18. CR10Vertical Sync Start Register19. CR11Vertical Sync End Register 20. CR12Vertical Display Enable End Register CR13Offset RegisterCount By CR146 CR176 Addressing Mode22. CR14Underline Location Register CR145 CR173 Address Incrementing Interval23. CR15Vertical Blanking Start Register 24. CR16Vertical Blanking End Register25. CR17CRT Mode Control Word Mode or Byte ModeCR146 CR176 Compatibility Mode Support Select Row Scan CounterDWord Mode Memory Address Counter Address BitsFrame Buffer Address Decoder CR17 bit 1=1 CR17 bit 1=0 CR17 bit 0=1 CR17 bit 0=026. CR18Line Compare Register 27. CR22Memory Read Latch Data Register29. CR30Extended Vertical Total Register 30. CR31Extended Vertical Display End Register 31. CR32Extended Vertical Sync Start Register 32. CR33Extended Vertical Blanking Start Register 33. CR35 Extended Horizontal Total Time Register 34. CR39Extended Horizontal Blank Time RegisterExtended Horizontal Total MSB that extends CR00 35. CR40Extended Start Address Register 36. CR41Extended Offset Register 37. CR42Extended Start Address High RegisterInterlace Enable 38. CR70Interlace Control Register39. CR80I/O Control 40. CR81Reserved 41. CR82Blink Rate ControlProgramming Interface Reserved Bits and Software CompatibilityOverview Instruction Use GC Register ProgrammingGC Instruction Streams Instruction Transport OverviewInstruction Parser Interrupt RingRing Buffers RB Ring Buffer RegistersCharacteristic Description Ring Buffer InitializationRing Buffer Use Batch Buffers Batch Buffer SequenceInstruction Arbitration Arbitration RationaleWait Instructions Batch Buffer Protected Mode Instruction Arbitration PointsInstruction Arbitration Rules Instruction Format Instruction Parser InstructionsInstructions Bits 3129 2824 210Graphics Controller Instructions Client InstructionClient Instruction Descriptions Instruction Parser InstructionsIntroduction DWord Bit DescriptionOpcode 01h Opcode 02hReserved MBZ Gfxcmdparserwaitforevent DWord BitDWord Bits Description Opcode 15h Reserved 00000hDwordlength 00h Instruction Target 14h Flip type 0 Synch flip, 1 Async flipDword Length 00h Opcode 16h Opcode 07hInstruction Target 11h Opcode 08hArbitration ON/OFF Instruction Target 12hWord Bits Description Gfxcmdparserbatchbuffer Instruction Target 30hInstructions BLTs To and From Cacheable MemoryBLT Engine Instructions Setupblt Instruction Target Opcode 00h Setup Background Color AllSetup Foreground Color SLB & TB only Dword Length 06hColor Depth Instruction Target Opcode 10hDword Length 07h Raster OperationInstruction Target Opcode 21h PixelbltInstruction Target Opcode 20h Destination X2 Coordinate Ending RightTextblt Instruction Target Opcode 22hDword Length 04h Immediate Data DW TEXTImmediateBLTInstruction Target Opcode 30h Immediate Data DWs 2 through Dwordlength DWLDword Length 03h ColorbltInstruction Target Opcode 40h Solid Pattern ColorPatblt Instruction Target Opcode 41hInstruction Target Opcode 42h Mono Pattern Transparency Mode 1 = transparency enabledMonopatblt Pattern Background ColorSrccopyblt Instruction Target Opcode 43hInstruction Target Opcode 44h LineSource Background Color Source Foreground ColorMono Source Transparency Mode 1 = transparency enabled Instruction Target Opcode 61hDestination Transparency Mode See BR00 definition FullbltInstruction Target Opcode 45h Fullmonosrcblt Destination Transparency ColorInstruction Target Opcode 46h Instruction Target Opcode 47h Dword Length 09h181 Instruction Target Opcode 48h Dword Length 0Ah183 BLT Engine Instruction Definitions 12.3.1. BR00-BLT Opcode and Control185 SolPat Rsvd Mono 187 12.3.3. BR02-Clip Rectangle Y1 Address 12.3.4. BR03-Clip Rectangle Y2 Address12.3.5. BR04-Clip Rectangle X1 3128 Reserved. Must be Zero 271612.3.6. BR05-Setup Expansion Background Color 12.3.7. BR06-Setup Expansion Foreground Color12.3.8. BR07-Setup Color Pattern Address 12.3.9. BR08-Destination X1 12.3.10. BR09-Destination Address and Destination Y1 Address 12.3.11. BR10-Destination Y2 AddressSource Pitch Offset or Monochrome Source Quadwords 12.3.13. BR12-Source Address 12.3.14. BR13-BLT Raster OP, Control, and Destination Pitch Increment/Decrement SelectSource Select Mode Dynamic Color Depth12.3.15. BR14-Destination Width & Height 12.3.16. BR15-Color Pattern Address 12.3.18. BR17-Pattern Expansion Foreground Color 3124 Reserved. Must be Zero 23012.3.20. BR19-Source Expansion Foreground Color SSLADD-Source Scan Line Address DSLH-Destination Scan Line HeightDSLRADD-Destination Scan Line Read Address 204 Axis Aligned Rectangles Rendering Engine InstructionsGfxprimitive Primitive Winding OrderPosition Mask BiasPrimitive Rendering Instruction Format Variable Length Vertex Formats for Rendering Instructions Vertex Attribute CommentsGfxvertex Gfxrenderstatevertexformat Block Type GfxblockRendering Block 1Eh Block Pattern FormatDWord Bits Vertical Motion Vector Precision 00 = 1/2 pixelPrediction Type 212 Non-pipelined State Variables Motion Vector FormatPrecision Format Range Gfxrenderstatemaptexels Gfxrenderstatemapcoordsets Opcode 1h Update Coordinate Set Index The valid range isNormalized Coordinate Set Mask 0 = Do not update 1 = Update Normalized Coordinate SetGfxrenderstatemapinfo Discrete Integrated Base Utilize Fence Tiled Surface WalkReserved 0h 3DstateMW 1DhDwordlength 2h Surface FormatColor Space Conversion Enable 1511221 Gfxrenderstatemapfilter Reserved 00h Mip Mode Filter Valid values are Opcode 2hGfxrenderstatemaplodlimits Opcode 3hTexture LOD Dither Weight Mask 0 = Do not update 1 = Update GfxrenderstatemaplodcontrolOpcode 4h Gfxrenderstatemappaletteload 3DStateMWNPNon-pipelined 1DhOpcode 82h Gfxrenderstatemapcolorblendstages Blend Equation DescriptionWrite result to Current Register or Accumulator Select Update Blending Stage Index The valid range is3DState24 00h Replicate Arg1 Alpha to Color ChannelsInvert Color Arg2 Gfxrenderstatemapalphablendstages 3DState24 01h Invert Alpha Arg1Invert Alpha Arg2 Gfxrenderstatecolorfactor Instruction 1hKill Pixel Mode GfxrenderstatecolorchromakeyKeyedPixelControl Write Mask 0 = Do not update 1 = Update Instruction 2hKeyedPixelControl Gfxrenderstatesrcdstblendmono No SpecularMonochrome Specular Full Color RGB 236 Opcode Source / Destination Blend State Alpha Reference State Mask 1 = Update 0 = Do Not Update Gfxrenderstatezbiasalphafuncref3DState24NP Non-pipelined 14h Gfxrenderstatelinewidthcullshade Mode Color Shade Mode State Mask 1 = Update 0 = Do Not Update Alpha Shade Mode State Mask 1 = Update 0 = Do Not UpdateSpecular Shade Mode State Mask 1 = Update 0 = Do Not Update 2824 3DState24 02hSpecular Enable State Mask 1 = Update 0 = Do Not Update Alpha Setup Enable Enable Mask 1 = Update 0 = Do Not UpdateColor Index Key Enable Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA1Buffer Write Enable Mask 1 = Update 0 = Do Not Update Specular Dither Enable Mask 1 = Update 0 = Do Not UpdateFrame Buffer Write Enable Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA2Gfxrenderstatefogcolor Gfxrenderstatedrawingrectangleinfo3DState24NP Non-pipelined 15h 3DStateMWNP Non-pipelined 1Dh Opcode 80h3DState16NP Non-pipelined 1Ch GfxrenderstatescissorenableScissor Rectangle Enable Mask 1 = Update 0 = Do Not Update Opcode 10hGfxrenderstatescissorrectangleinfo Opcode 81hStipple Pattern Opcode 83hStipple Pattern Gfxrenderstateantialiasing Gfxrenderstateprovokingvtxpixelization Rule Vertex SequenceSmall Triangle Filter Enable Mask Pixelization Rule MaskGfxrenderstatedestbuffervariables Opcode 85hDest Buffer Format 0h = Any 8-bit Surface Programming Hints/Rules Drawing and Scissor RectanglesColor Calculator 255 256 Clock Control Registers Programming NotesDCLK0D-Display Clock 0 Divisor Register Example Programming Sequence DCLK2DCLK1D-Display Clock 1 Divisor Register DCLK2D-Display Clock 2 Divisor Register LCDCLKD-LCD Clock Divisor Register DCLK0DS-Display & LCD Clock Divisor Select Register Post Divisor Select LCD ClockReserved VCO Loop Divide LCD Clock Post Divisor Select clock VCO Loop Divide clockPWRCLKC-Power Management and Miscellaneous Clock Control Internal DAC EnableOverlay Registers Register/Instruction Category Comment15.1. OV0ADD-Overlay 0 Register Update Address Register Updating Register ValuesDOV0STA-Display/Overlay 0 Status Register Gamma Correction GAMC50-Gamma Correction RegistersRed Green BlueMathematical Gamma Correction For Overlay Three timesGamma Correction Theory Of Operation Latch AddressGamma Hardware Implementation OBUF0Y-Overlay Buffer 0 Y Pointer Register Memory Offset RegistersOverlay Buffer Pointer Registers Format AlignmentOBUF1Y-Overlay Buffer 1 Y Pointer Register OBUF0U-Overlay Buffer 0 U Pointer RegisterOBUF0V-Overlay Buffer 0 V Pointer Register OBUF1U-Overlay Buffer 1 U Pointer RegisterBit Descriptiont Overlay Stride Registers OBUF1V-Overlay Buffer 1 V Pointer Register15.4.2.1. OV0STRIDE-Overlay 0 Stride Register Overlay Initial Phase Registers YRGBVPH-Y/RGB Vertical Phase RegisterUVVPH-UV Vertical Phase Register HORZPH-Horizontal Phase RegisterINITPH-Initial Phase Register Overlay Destination Window Position/Size Registers DWINPOS-Destination Window Position RegisterDWINSZ-Destination Window Size Register Overlay Source Size Registers SWID-Source Width RegisterSWIDQW-Source Width In QWords Register SHEIGHT-Source Height Register Overlay Scale Factor Registers YRGBSCALE-Y/RGB Scale Factor RegisterUVSCALE-UV Scale Factor Register Overlay Color Correction Registers 15.4.7.1. OV0CLRC0-Overlay 0 Color Correction 0 Register15.4.7.2. OV0CLRC1-Overlay 0 Color Correction 1 Register Overlay Destination Color Key Registers DCLRKV-Destination Color Key Value RegisterDestination Constant Alpha Blend Enable Always Constant Alpha Blend EnableDCLRKM-Destination Color Key Mask Register Overlay Source Color Key Registers SCLRKVH-Source Color Key Value High RegisterSCLRKVL-Source Color Key Value Low Register SCLRKM-Source Color Key Mask RegisterSource Constant Alpha Blend Enable Overlay Configuration Registers 15.4.10.1. OV0CONF-Overlay Configuration Register15.4.11. OV0CMD-Overlay Command Register Vertical Chrominance Filter. Vertical Chrominance Filter Vertical Luminance Filter. Vertical Luminance FilterManual flip command Source FormatAutomatic flipping 297 Overlay Alpha Blend Window Position/Size Registers AWINPOS-Alpha Blend Window Position RegisterOverlay Flip Instruction AWINSZ-Alpha Blend Window Size Register300 Instruction, Memory, and Interrupt Control Registers Instruction Control RegistersFENCE-Graphics Memory Fence Table Registers Fence size Reserved for address bits 31 downtoTile walk Fence PitchPGTBLCTL-Page Table Control Register Normal Invalidation MechanismPGTBLER-Page Table Error Register Error Type PGTBLERRMSK-Page Table Error Mask Register Overlay Page Table Error Mask Buffer Unit Page Table Error MaskCommand Streamer DMA Page Table Error Mask Display Page Table Error MaskRINGBUF-Ring Buffer Registers Intel 810 Chipset and Intel815 Chipset ErrataReserved Ring Buffer ValidHWSPGA-Hardware Status Page Address Register DWord Description OffsetIPEIR-Instruction Parser Error Identification Register debug IPEHR-Instruction Parser Error Header Register debugThis read only register reports engine done signals INSTDONE-Instruction Stream Interface Done RegisterNOPID-NOP Identification Register INSTPM-Instruction Parser Mode Register Disable State Variable UpdatesINSTPS-Instruction Parser State Register debug Cscpr State Machine Command Parser BBPPTR-Batch Buffer Parser Pointer Register debug ABBSTR-Active Batch Buffer Start Address Register debugABBEND-Active Batch Buffer End Address Register debug DMAFADD-DMA Engine Fetch Address debugCurrent DMA Address Reserved User of the DMA Engine Graphics Address Translation Mode MEMMODE-Memory Interface Mode Register debugReserved Host Graphics Prefetch Mode Instruction Fifo Debug ModeInterrupt Control Registers Bit Definition For Interrupt Control Registers321 HWSTAM-Hardware Status Mask Register IER-Interrupt Enable Register Interrupt Enables. See TableIIR-Interrupt Identity Register Interrupt Identity. See. TableIMR-Interrupt Mask Register Interrupt Mask Bits. See. TableISR-Interrupt Status Register Error Identity, Mask and Status Registers Table Error handling in Intel 815 ChipsetResetting the Page Table Error Table ErrorEIR-Error Identity Register EMR-Error Mask RegisterESR-Error Status Register Display Interface Control FWBLC-FIFO Watermark and Burst Length Control332 LCD / TV-Out Register Description HTOTAL-Horizontal Total RegisterHBLANK-Horizontal Blank Register HSYNC-Horizontal Sync Register VTOTAL-Vertical Total Register VBLANK-Vertical Blank Register VSYNC-Vertical Sync Register LCD / TV-Out Enable LCDTVC-LCD/TV-Out Control RegisterSync Polarity Control Fpvsync Control FP Vesa VGA ModeFP / 740 Data Ordering Fphsync ControlActive Data Order Border EnableFphsync Output Control Active Data PolarityOVRACT-Overlay Active Register BCLRPAT- Border Color Pattern RegisterLocal Memory Interface DRT-DRAM Row TypeDRAMCL-DRAM Control Low Reserved Paging Mode Control PMCBit RAS#-to-CAS# delay t RCD Bit RAS# act. To precharge t RAS Refresh to RAS# act. t RCDRAMCH-DRAM Control High 346 19. I/O Control Registers HVSYNC-HSYNC/VSYNC Control RegisterHSYNC/VSYNC Control1916 Gpio Registers GPIOAGeneral Purpose I/O Control Register aValue .bit GPIOBGeneral Purpose I/O Control Register B 351 352 Display And Cursor Registers DISPSL-Display Scan Line CountLine Counter for Display DISPSLC-Display Scan Line Count Range Compare Inclusive / ExclusiveOverlay path Gamma Enable. See note PIXCONF-Pixel Pipeline ConfigurationReserved Display path Graphics Gamma Enable. See note Pixel Pipeline ControlEnable Extended Status Read Mode Display Color ModeBit DAC Enable CRT Overscan ColorBLTCNTL-BLT Control GUI ModeTransition from VGA modes to hires mode or opposite SWF13-Software Flag RegistersDPLYBASE-Display Base Address Register Display Line Compare Enable Reserved Flat Panel Hot Plug Detect EnableVertical Sync Status Enable DPLYSTAS-Display Status Select RegisterOverlay Registers Updated Status Vertical Blank EnableOverlay Registers Upated Enable Vertical Sync StatusHardware Cursor CURCNTR-Cursor Control RegisterReserved Cursor Coordinate System Origin Select CURBASE-Cursor Base Address Register CURPOS-Cursor Position RegisterAppendix a Mode Parameters Parameters for Screen Resolution/Refresh Rate 320x20070Hz = Parameters for Screen Resolution/Refresh Rate 320x24070Hz = Parameters for Screen Resolution/Refresh Rate 352X48070Hz = Parameters for Screen Resolution/Refresh Rate 352X57670Hz = Parameters for Screen Resolution/Refresh Rate 400x30070Hz = Parameters for Screen Resolution/Refresh Rate 512X38470Hz = Parameters for Screen Resolution/Refresh Rate 640x35085Hz = Parameters for Screen Resolution/Refresh Rate 640x40070Hz = Parameters for Screen Resolution/Refresh Rate 640x40085Hz = Parameters for Screen Resolution/Refresh Rate 640x48060Hz = Parameters for Screen Resolution/Refresh Rate 640x48070Hz = Parameters for Screen Resolution/Refresh Rate 640x48072Hz = Parameters for Screen Resolution/Refresh Rate 640x48075Hz = Parameters for Screen Resolution/Refresh Rate 640x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x40085Hz = Parameters for Screen Resolution/Refresh Rate 720x48060Hz = Parameters for Screen Resolution/Refresh Rate 720x48075Hz = Parameters for Screen Resolution/Refresh Rate 720x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x57660Hz = Parameters for Screen Resolution/Refresh Rate 720x57675Hz = Parameters for Screen Resolution/Refresh Rate 720x57685Hz = Parameters for Screen Resolution/Refresh Rate 800x60056Hz = Parameters for Screen Resolution/Refresh Rate 800x60060Hz = Parameters for Screen Resolution/Refresh Rate 800x60070Hz = Parameters for Screen Resolution/Refresh Rate 800x60072Hz = Parameters for Screen Resolution/Refresh Rate 800x60075Hz = Parameters for Screen Resolution/Refresh Rate 800x60085Hz = Parameters for Screen Resolution/Refresh Rate 854X48060Hz = Parameters for Screen Resolution/Refresh Rate 854X48075Hz = Parameters for Screen Resolution/Refresh Rate 854X48085Hz = 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 Intel around the world