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Intel 815 manual Gfxrenderstatemaptexels

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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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13.5.GFXRENDERSTATE_MAP_TEXELS

The Mapping Engine is capable of generating at most two texels per pixel. The texels may be obtained from two separate maps or the same map using different u,v coordinates. The binding between the texels which are generated by the engine and the coordinate set and the map information state is specified with this instruction. The texels are generated in the order specified by the Texel Index. If no texel is enabled, texture mapping is disabled and this is the default condition. If one of the two texels is enabled, one texture coordinate will be used for texture mapping. If both texels are enabled, both texture coordinates will be used for texture mapping.

Figure 31. State Variable Relationships

Coordinate Sets

Texels

Map Information

Blending Stages

DWord	Bit	Description

0	31:29	Client : 03h – Rendering Engine

	28:24	3DState16 : 1Ch

	23:19	Opcode : 0h

	18:16	Reserved: 00h (Additional Texels)

	15	Texel 1 State Variable Mask : 0 = Do not update; 1 = Update

	14	Texel 1 Enable :
		0 = Disable (default)
		1 = Enable

	13:12	Reserved: 00h (Additional Coordinate Sets)

	11	Texel 1 Coordinate Set Index : Index to the Coordinate Set.
	10:9	Reserved: 00h (Addition Map Information)

	8	Texel 1 Map Information Index : Index to the Map Information.
	7	Texel 0 State Variable Mask : 0 = Do not update; 1 = Update

	6	Texel 0 Enable :
		0 = Disable (default)
		1 = Enable

	5:4	Reserved: 00h (Additional Coordinate Sets)
	3	Texel 0 Coordinate Set Index : Index to the Coordinate Set.

	2:1	Reserved: 00h (Addition Map Information)
0	0	Texel 0 Map Information Index : Index to the Map Information.

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Intel 815 manual Gfxrenderstatemaptexels

Contents

Intel 815 Chipset Graphics Controller Programmer’s Reference Manual PRM Intel 815 Chipset Graphics Controller PRM, Rev Contents 100 106 141 Monosrccopyimmediateblt Gfxrenderstatemaplodlimits 15.4.3.3 HORZPH-Horizontal Phase Register 279 15.4.3.4 16.2.5 Figures Tables Rev Revision HistoryDate This page is intentionally left blank Terminology IntroductionTerm Description Reference Documents MCH Intel 815 Chipset Overview I/O Controller Hub Intel 82815 Chipset Gmch Overview Intel 82815 Chipset Gmch Block Diagram Host Interface System Memory Interface Data Rate Signaling LevelMultiplexed AGP and Display Cache Interface Hub Interface Intel 82815 Chipset Gmch Integrated Graphics Support System Clocking Gmch Power DeliveryThree PCI Devices on Gmch Front Side Bus System Memory Display Cache Interface Supported Single Monitor and Multi-monitor Configurations Multi-Mode Capability Requirements Configuration Single Monitor Multi-monitor Device Mode Auto-Detect Flowchart System Startup Software Start-Up Sequence Graphics Driver Startup Switching Device modes System Address Map System Memory Space Memory and I/O Space Registers Graphics Controller Register Memory and I/O Map Reserved 50000h−5FFFFh. Reserved in the Intel 815 chipset VGA and VGA Extended Registers Address Offset Symbol Register Name AccessGC Register Memory Address Map Instruction and Interrupt Control Registers 01000h −02FFFh Instpm OV0ADD Ssladd VGA and Extended VGA Register Map Display and Cursor Control Registers 70000h-7FFFFh VGA and Extended VGA I/O and Memory Register Map Address Register Name Read Register Name Write 2D Registers Index Sym Description Indirect VGA and Extended VGA Register IndicesIndex Sym Register Name 2D Attribute Controller Registers 3C0h / 3C1h CR0F Graphics Address Translation Memory Buffers for GC’s Instruction Interface GTT Graphics Translation Table GTT Range Definition This page is intentionally left blank Initialization Sequence Basic Initialization ProceduresVendor Id Device Id PCI Device Characteristics Hardware Detection Probe Frame Buffer Initialization Color vs. Monochrome Monitors Hardware Register InitializationHardware State Protect Registers Locking and Unlocking Saving the Hardware State Restoring the Hardware State Intel 815 Chipset Graphics Controller PRM, Rev Intel 815 Chipset Graphics Controller PRM, Rev This page is intentionally left blank Blt Engine Programming When the Source and Destination Locations OverlapBLT Engine Programming Considerations Source Bblt3.vsd Destination Source Bblt4.vsd Basic Graphics Data Considerations Contiguous vs. Discontinuous Graphics Data Source Data Monochrome Source Data Pattern Data Pattern Data -- Always an 8x8 Array of Pixels Bpp Pattern Data -- Occupies 64 Bytes 8 quadwords Destination Data BLT Programming Examples Pattern Fill -- a Very Simple BLT Pattern Data for Example Pattern Fill BLT Results of Example Pattern Fill BLT Drawing Characters Using a Font Stored in System Memory On-Screen Destination for Example Character Drawing BLT Intel 815 Chipset Graphics Controller PRM, Rev Results of Example Character Drawing BLT Smram Registers Initialization RegistersStandard VGA Registers SMRAM-System Management RAM Control Register Device Bit Description RAM Initialization and Usage of Stolen Memory LCD/TV-Out Clock Control and Power Management RegistersDisplay and Cursor Control Registers Graphics Controller Registers 3CEh / 3CFh CRT Controller Registers 3B4h/3D4h/3B5h/3D5h Initialization Values for VGA Registers MSR GR01 00h This page is intentionally left blank Frame Buffer Access Intel 815 Chipset Graphics Controller PRM, Rev Name Function Read Write Memory VGA and Extended VGA RegistersGeneral Control & Status Registers Offset 1. ST00Input Status Bit Bit Descriptions Display Enable OutputST01Input Status Vertical Retrace/Video FCRFeature Control Reserved. Read as Vsync Control CRT VSync Polarity MSRMiscellaneous OutputCRT HSync Polarity Sequencer Registers SRXSequencer Index 2. SR00Sequencer Reset 3. SR01Clocking Mode Shift 4. SR02Plane/Map Mask Bit 32 Map Number Table Location 5. SR03Character FontBit 10,4 Map Number Table Location 6. SR04Memory Mode Register Made according to the value of the Plane Mask Register SR02 GRXGRX Graphics Controller Index Register 7. SR07Horizontal Character Counter ResetGraphics Controller Registers Bit Description Horizontal Character Counter 2. GR00Set/Reset Register 3. GR01Enable Set/Reset Register 4. GR02Color Compare Register 5. GR03Data Rotate Register 7. GR05Graphics Mode Register 6. GR04Read Plane Select Register Bits 65=01 Bits 65=00Bits 65=1x Read Mode Odd/Even ModeWrite Mode 8. GR06Miscellaneous Register Graphics/Text ModeBit 10. GR08Bit Mask Register 9. GR07Color Don’t Care RegisterBit Mask 11. GR10Address Mapping Reserved To Local Memory EnablePacked Mode Enable VGA Buffer/Memory Map Select 12. GR11Page Selector Supported Memory Offset Address 3CFh Index=14h-1fh Default Attribute 13. GR141FSoftware Flags Attribute Controller Registers ARXAttribute Controller Index Register Palette Bits P5, P4 Select 2. AR000FPalette Registers 0F3. AR10Mode Control Register Pixel Width/Clock Select Graphics/Alphanumeric Mode Enable Blinking/Select Background IntensityEnable Line Graphics Character Code Pixel Panning Compatibility 4. AR11Overscan Color Register 5. AR12Memory Plane Enable RegisterBit 54 ST01 Bit Pixel Text Color 6. AR13Horizontal Pixel Panning RegisterReserved Pixel Text Graphics VGA Color Palette Registers 7. AR14Color Select Register DACMASKPixel Data Mask Register DACWXPalette Write Index Register DACSTATEDAC State RegisterDACRXPalette Read Index Register Bits Index Register Indicated CRT Controller Register DACDATAPalette Data Register Display Fields and Dimensions CRxx Control Registers CRXCRT Controller Index Register 2. CR00Horizontal Total Register 3. CR01Horizontal Display Enable End Register4. CR02Horizontal Blanking Start Register 5. CR03Horizontal Blanking End Register Bit Amount of Delay6. CR04Horizontal Sync Start Register 7. CR05Horizontal Sync End Register 8. CR06Vertical Total Register 9. CR07Overflow Register 115 116 10. CR08Preset Row Scan Register Double Scanning Enable 11. CR09Maximum Scan Line Register 12. CR0AText Cursor Start Register 13. CR0BText Cursor End Register 14. CR0CStart Address High Register 15. CR0DStart Address Low Register 16. CR0EText Cursor Location High Register 17. CR0FText Cursor Location Low Register 18. CR10Vertical Sync Start Register 19. CR11Vertical Sync End Register 20. CR12Vertical Display Enable End Register CR13Offset Register Count By CR146 CR176 Addressing Mode22. CR14Underline Location Register CR145 CR173 Address Incrementing Interval 23. CR15Vertical Blanking Start Register 24. CR16Vertical Blanking End Register Word Mode or Byte Mode 25. CR17CRT Mode ControlCR146 CR176 Compatibility Mode Support Select Row Scan Counter DWord Mode Memory Address Counter Address Bits Frame Buffer Address Decoder CR17 bit 1=1 CR17 bit 1=0 CR17 bit 0=1 CR17 bit 0=0 26. CR18Line Compare Register 27. CR22Memory Read Latch Data Register 29. CR30Extended Vertical Total Register 30. CR31Extended Vertical Display End Register 31. CR32Extended Vertical Sync Start Register 32. CR33Extended Vertical Blanking Start Register 34. CR39Extended Horizontal Blank Time Register 33. CR35 Extended Horizontal Total Time RegisterExtended Horizontal Total MSB that extends CR00 35. CR40Extended Start Address Register 36. CR41Extended Offset Register 37. CR42Extended Start Address High Register 38. CR70Interlace Control Register Interlace Enable39. CR80I/O Control 40. CR81Reserved 41. CR82Blink Rate Control Reserved Bits and Software Compatibility Programming InterfaceOverview Instruction Use GC Register ProgrammingGC Instruction Streams Instruction Transport Overview Instruction Parser Interrupt Ring Ring Buffers RB Ring Buffer Registers Ring Buffer Initialization Characteristic DescriptionRing Buffer Use Batch Buffers Batch Buffer Sequence Arbitration Rationale Instruction ArbitrationWait Instructions Instruction Arbitration Points Batch Buffer Protected ModeInstruction Arbitration Rules Instruction Parser Instructions Instruction FormatInstructions Bits 3129 2824 210 Graphics Controller Instructions Client Instruction Client Instruction Descriptions Instruction Parser InstructionsIntroduction DWord Bit Description Opcode 02h Opcode 01hReserved MBZ Gfxcmdparserwaitforevent DWord Bit DWord Bits Description Reserved 00000h Opcode 15hDwordlength 00h Flip type 0 Synch flip, 1 Async flip Instruction Target 14hDword Length 00h Opcode 16h Opcode 07h Instruction Target 11h Opcode 08hArbitration ON/OFF Instruction Target 12h Word Bits Description Gfxcmdparserbatchbuffer Instruction Target 30h BLTs To and From Cacheable Memory InstructionsBLT Engine Instructions Setupblt Instruction Target Opcode 00h Setup Background Color AllSetup Foreground Color SLB & TB only Dword Length 06h Color Depth Instruction Target Opcode 10hDword Length 07h Raster Operation Instruction Target Opcode 21h PixelbltInstruction Target Opcode 20h Destination X2 Coordinate Ending Right Instruction Target Opcode 22h TextbltDword Length 04h Immediate Data DW TEXTImmediateBLTInstruction Target Opcode 30h Immediate Data DWs 2 through Dwordlength DWL Dword Length 03h ColorbltInstruction Target Opcode 40h Solid Pattern Color Patblt Instruction Target Opcode 41h Instruction Target Opcode 42h Mono Pattern Transparency Mode 1 = transparency enabledMonopatblt Pattern Background Color Srccopyblt Instruction Target Opcode 43h Instruction Target Opcode 44h Line Source Background Color Source Foreground Color Mono Source Transparency Mode 1 = transparency enabled Instruction Target Opcode 61h Fullblt Destination Transparency Mode See BR00 definitionInstruction Target Opcode 45h Fullmonosrcblt Destination Transparency Color Instruction Target Opcode 46h Instruction Target Opcode 47h Dword Length 09h 181 Instruction Target Opcode 48h Dword Length 0Ah 183 BLT Engine Instruction Definitions 12.3.1. BR00-BLT Opcode and Control 185 SolPat Rsvd Mono 187 12.3.3. BR02-Clip Rectangle Y1 Address 12.3.4. BR03-Clip Rectangle Y2 Address 12.3.5. BR04-Clip Rectangle X1 3128 Reserved. Must be Zero 2716 12.3.6. BR05-Setup Expansion Background Color 12.3.7. BR06-Setup Expansion Foreground Color 12.3.8. BR07-Setup Color Pattern Address 12.3.9. BR08-Destination X1 12.3.10. BR09-Destination Address and Destination Y1 Address 12.3.11. BR10-Destination Y2 Address Source Pitch Offset or Monochrome Source Quadwords 12.3.13. BR12-Source Address 12.3.14. BR13-BLT Raster OP, Control, and Destination Pitch Increment/Decrement Select Source Select Mode Dynamic Color Depth 12.3.15. BR14-Destination Width & Height 12.3.16. BR15-Color Pattern Address 12.3.18. BR17-Pattern Expansion Foreground Color 3124 Reserved. Must be Zero 230 12.3.20. BR19-Source Expansion Foreground Color SSLADD-Source Scan Line Address DSLH-Destination Scan Line Height DSLRADD-Destination Scan Line Read Address 204 Axis Aligned Rectangles Rendering Engine InstructionsGfxprimitive Primitive Winding Order Bias Position MaskPrimitive Rendering Instruction Format Variable Length Vertex Formats for Rendering Instructions Vertex Attribute Comments Gfxvertex Gfxrenderstatevertexformat Block Type GfxblockRendering Block 1Eh Block Pattern Format Vertical Motion Vector Precision 00 = 1/2 pixel DWord BitsPrediction Type 212 Motion Vector Format Non-pipelined State VariablesPrecision Format Range Gfxrenderstatemaptexels Gfxrenderstatemapcoordsets Opcode 1h Update Coordinate Set Index The valid range isNormalized Coordinate Set Mask 0 = Do not update 1 = Update Normalized Coordinate Set Gfxrenderstatemapinfo Discrete Integrated Base Utilize Fence Tiled Surface Walk Reserved 0h 3DstateMW 1DhDwordlength 2h Surface Format Color Space Conversion Enable 1511 221 Gfxrenderstatemapfilter Reserved 00h Mip Mode Filter Valid values are Opcode 2h Gfxrenderstatemaplodlimits Opcode 3h Gfxrenderstatemaplodcontrol Texture LOD Dither Weight Mask 0 = Do not update 1 = UpdateOpcode 4h 3DStateMWNPNon-pipelined 1Dh GfxrenderstatemappaletteloadOpcode 82h Gfxrenderstatemapcolorblendstages Blend Equation Description Write result to Current Register or Accumulator Select Update Blending Stage Index The valid range is3DState24 00h Replicate Arg1 Alpha to Color Channels Invert Color Arg2 Gfxrenderstatemapalphablendstages Invert Alpha Arg1 3DState24 01hInvert Alpha Arg2 Gfxrenderstatecolorfactor Instruction 1h Kill Pixel Mode Gfxrenderstatecolorchromakey Instruction 2h KeyedPixelControl Write Mask 0 = Do not update 1 = UpdateKeyedPixelControl No Specular GfxrenderstatesrcdstblendmonoMonochrome Specular Full Color RGB 236 Opcode Source / Destination Blend State Gfxrenderstatezbiasalphafuncref Alpha Reference State Mask 1 = Update 0 = Do Not Update3DState24NP Non-pipelined 14h Gfxrenderstatelinewidthcullshade Mode Color Shade Mode State Mask 1 = Update 0 = Do Not Update Alpha Shade Mode State Mask 1 = Update 0 = Do Not UpdateSpecular Shade Mode State Mask 1 = Update 0 = Do Not Update 2824 3DState24 02h Specular Enable State Mask 1 = Update 0 = Do Not Update Alpha Setup Enable Enable Mask 1 = Update 0 = Do Not UpdateColor Index Key Enable Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA1 Buffer Write Enable Mask 1 = Update 0 = Do Not Update Specular Dither Enable Mask 1 = Update 0 = Do Not UpdateFrame Buffer Write Enable Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA2 Gfxrenderstatedrawingrectangleinfo Gfxrenderstatefogcolor3DState24NP Non-pipelined 15h 3DStateMWNP Non-pipelined 1Dh Opcode 80h 3DState16NP Non-pipelined 1Ch GfxrenderstatescissorenableScissor Rectangle Enable Mask 1 = Update 0 = Do Not Update Opcode 10h Gfxrenderstatescissorrectangleinfo Opcode 81h Opcode 83h Stipple PatternStipple Pattern Gfxrenderstateantialiasing Gfxrenderstateprovokingvtxpixelization Rule Vertex Sequence Small Triangle Filter Enable Mask Pixelization Rule Mask Gfxrenderstatedestbuffervariables Opcode 85h Dest Buffer Format 0h = Any 8-bit Surface Programming Hints/Rules Drawing and Scissor Rectangles Color Calculator 255 256 Clock Control Registers Programming Notes DCLK0D-Display Clock 0 Divisor Register Example Programming Sequence DCLK2 DCLK1D-Display Clock 1 Divisor Register DCLK2D-Display Clock 2 Divisor Register LCDCLKD-LCD Clock Divisor Register Post Divisor Select LCD Clock DCLK0DS-Display & LCD Clock Divisor Select RegisterReserved VCO Loop Divide LCD Clock Post Divisor Select clock VCO Loop Divide clock PWRCLKC-Power Management and Miscellaneous Clock Control Internal DAC Enable Overlay Registers Register/Instruction Category Comment 15.1. OV0ADD-Overlay 0 Register Update Address Register Updating Register Values DOV0STA-Display/Overlay 0 Status Register Gamma Correction GAMC50-Gamma Correction Registers Red Green Blue Mathematical Gamma Correction For Overlay Three times Gamma Correction Theory Of Operation Latch Address Gamma Hardware Implementation OBUF0Y-Overlay Buffer 0 Y Pointer Register Memory Offset RegistersOverlay Buffer Pointer Registers Format Alignment OBUF1Y-Overlay Buffer 1 Y Pointer Register OBUF0U-Overlay Buffer 0 U Pointer Register OBUF1U-Overlay Buffer 1 U Pointer Register OBUF0V-Overlay Buffer 0 V Pointer RegisterBit Descriptiont OBUF1V-Overlay Buffer 1 V Pointer Register Overlay Stride Registers15.4.2.1. OV0STRIDE-Overlay 0 Stride Register Overlay Initial Phase Registers YRGBVPH-Y/RGB Vertical Phase Register UVVPH-UV Vertical Phase Register HORZPH-Horizontal Phase Register INITPH-Initial Phase Register DWINPOS-Destination Window Position Register Overlay Destination Window Position/Size RegistersDWINSZ-Destination Window Size Register Overlay Source Size Registers SWID-Source Width Register SWIDQW-Source Width In QWords Register SHEIGHT-Source Height Register Overlay Scale Factor Registers YRGBSCALE-Y/RGB Scale Factor Register UVSCALE-UV Scale Factor Register 15.4.7.1. OV0CLRC0-Overlay 0 Color Correction 0 Register Overlay Color Correction Registers15.4.7.2. OV0CLRC1-Overlay 0 Color Correction 1 Register Overlay Destination Color Key Registers DCLRKV-Destination Color Key Value Register Always Constant Alpha Blend Enable Destination Constant Alpha Blend EnableDCLRKM-Destination Color Key Mask Register Overlay Source Color Key Registers SCLRKVH-Source Color Key Value High Register SCLRKVL-Source Color Key Value Low Register SCLRKM-Source Color Key Mask Register Source Constant Alpha Blend Enable Overlay Configuration Registers 15.4.10.1. OV0CONF-Overlay Configuration Register 15.4.11. OV0CMD-Overlay Command Register Vertical Chrominance Filter. Vertical Chrominance Filter Vertical Luminance Filter. Vertical Luminance Filter Source Format Manual flip commandAutomatic flipping 297 Overlay Alpha Blend Window Position/Size Registers AWINPOS-Alpha Blend Window Position Register Overlay Flip Instruction AWINSZ-Alpha Blend Window Size Register 300 Instruction Control Registers Instruction, Memory, and Interrupt Control RegistersFENCE-Graphics Memory Fence Table Registers Fence size Reserved for address bits 31 downtoTile walk Fence Pitch PGTBLCTL-Page Table Control Register Normal Invalidation Mechanism PGTBLER-Page Table Error Register Error Type PGTBLERRMSK-Page Table Error Mask Register Overlay Page Table Error Mask Buffer Unit Page Table Error MaskCommand Streamer DMA Page Table Error Mask Display Page Table Error Mask RINGBUF-Ring Buffer Registers Intel 810 Chipset and Intel815 Chipset Errata Reserved Ring Buffer Valid HWSPGA-Hardware Status Page Address Register DWord Description Offset IPEIR-Instruction Parser Error Identification Register debug IPEHR-Instruction Parser Error Header Register debug This read only register reports engine done signals INSTDONE-Instruction Stream Interface Done Register NOPID-NOP Identification Register INSTPM-Instruction Parser Mode Register Disable State Variable Updates INSTPS-Instruction Parser State Register debug Cscpr State Machine Command Parser BBPPTR-Batch Buffer Parser Pointer Register debug ABBSTR-Active Batch Buffer Start Address Register debug DMAFADD-DMA Engine Fetch Address debug ABBEND-Active Batch Buffer End Address Register debugCurrent DMA Address Reserved User of the DMA Engine Graphics Address Translation Mode MEMMODE-Memory Interface Mode Register debugReserved Host Graphics Prefetch Mode Instruction Fifo Debug Mode Interrupt Control Registers Bit Definition For Interrupt Control Registers 321 HWSTAM-Hardware Status Mask Register IER-Interrupt Enable Register Interrupt Enables. See Table IIR-Interrupt Identity Register Interrupt Identity. See. Table IMR-Interrupt Mask Register Interrupt Mask Bits. See. Table ISR-Interrupt Status Register Error Identity, Mask and Status Registers Table Error handling in Intel 815 Chipset Resetting the Page Table Error Table Error EIR-Error Identity Register EMR-Error Mask Register ESR-Error Status Register Display Interface Control FWBLC-FIFO Watermark and Burst Length Control 332 LCD / TV-Out Register Description HTOTAL-Horizontal Total Register HBLANK-Horizontal Blank Register HSYNC-Horizontal Sync Register VTOTAL-Vertical Total Register VBLANK-Vertical Blank Register VSYNC-Vertical Sync Register LCDTVC-LCD/TV-Out Control Register LCD / TV-Out EnableSync Polarity Control Fpvsync Control FP Vesa VGA ModeFP / 740 Data Ordering Fphsync Control Active Data Order Border EnableFphsync Output Control Active Data Polarity OVRACT-Overlay Active Register BCLRPAT- Border Color Pattern Register Local Memory Interface DRT-DRAM Row Type DRAMCL-DRAM Control Low Reserved Paging Mode Control PMCBit RAS#-to-CAS# delay t RCD Bit RAS# act. To precharge t RAS Refresh to RAS# act. t RC DRAMCH-DRAM Control High 346 HVSYNC-HSYNC/VSYNC Control Register 19. I/O Control RegistersHSYNC/VSYNC Control1916 Gpio Registers GPIOAGeneral Purpose I/O Control Register a Value .bit GPIOBGeneral Purpose I/O Control Register B 351 352 DISPSL-Display Scan Line Count Display And Cursor RegistersLine Counter for Display DISPSLC-Display Scan Line Count Range Compare Inclusive / Exclusive Overlay path Gamma Enable. See note PIXCONF-Pixel Pipeline ConfigurationReserved Display path Graphics Gamma Enable. See note Pixel Pipeline Control Enable Extended Status Read Mode Display Color ModeBit DAC Enable CRT Overscan Color BLTCNTL-BLT Control GUI ModeTransition from VGA modes to hires mode or opposite SWF13-Software Flag Registers DPLYBASE-Display Base Address Register Display Line Compare Enable Reserved Flat Panel Hot Plug Detect EnableVertical Sync Status Enable DPLYSTAS-Display Status Select Register Overlay Registers Updated Status Vertical Blank EnableOverlay Registers Upated Enable Vertical Sync Status CURCNTR-Cursor Control Register Hardware CursorReserved Cursor Coordinate System Origin Select CURBASE-Cursor Base Address Register CURPOS-Cursor Position Register Appendix a Mode Parameters Parameters for Screen Resolution/Refresh Rate 320x20070Hz = Parameters for Screen Resolution/Refresh Rate 320x24070Hz = Parameters for Screen Resolution/Refresh Rate 352X48070Hz = Parameters for Screen Resolution/Refresh Rate 352X57670Hz = Parameters for Screen Resolution/Refresh Rate 400x30070Hz = Parameters for Screen Resolution/Refresh Rate 512X38470Hz = Parameters for Screen Resolution/Refresh Rate 640x35085Hz = Parameters for Screen Resolution/Refresh Rate 640x40070Hz = Parameters for Screen Resolution/Refresh Rate 640x40085Hz = Parameters for Screen Resolution/Refresh Rate 640x48060Hz = Parameters for Screen Resolution/Refresh Rate 640x48070Hz = Parameters for Screen Resolution/Refresh Rate 640x48072Hz = Parameters for Screen Resolution/Refresh Rate 640x48075Hz = Parameters for Screen Resolution/Refresh Rate 640x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x40085Hz = Parameters for Screen Resolution/Refresh Rate 720x48060Hz = Parameters for Screen Resolution/Refresh Rate 720x48075Hz = Parameters for Screen Resolution/Refresh Rate 720x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x57660Hz = Parameters for Screen Resolution/Refresh Rate 720x57675Hz = Parameters for Screen Resolution/Refresh Rate 720x57685Hz = Parameters for Screen Resolution/Refresh Rate 800x60056Hz = Parameters for Screen Resolution/Refresh Rate 800x60060Hz = Parameters for Screen Resolution/Refresh Rate 800x60070Hz = Parameters for Screen Resolution/Refresh Rate 800x60072Hz = Parameters for Screen Resolution/Refresh Rate 800x60075Hz = Parameters for Screen Resolution/Refresh Rate 800x60085Hz = Parameters for Screen Resolution/Refresh Rate 854X48060Hz = Parameters for Screen Resolution/Refresh Rate 854X48075Hz = Parameters for Screen Resolution/Refresh Rate 854X48085Hz = 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 Intel around the world