Intel 815 manual Fphsync Output Control, Border Enable, Active Data Order, Active Data Polarity

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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Bit		Description
8	FPHSYNC Output Control.
	1	= Tristates the FPHSYNC pin.
	0	= FPHSYNC is active unless LCD / TV Out Enable is deasserted.
7	Border Enable.
	1	= Border to the LCD / TV encoder is enabled.
	0	= Border to the LCD / TV encoder is disabled.
6	Active Data Order.
	1	= Reversed ½ pixel data ordering: G[3:0] ‘ B[7:0] followed by R[7:0] ‘ G[7:4].
	0	= Normal ½ pixel data ordering: R[7:0] ‘ G[7:4] followed by G[3:0] ‘ B[7:0].
5	Active Data Polarity.
	1	= Inverted Pixel Data
	0	= Normal Pixel Data
4	VSYNC Polarity Control. When the LCD / TV timing generator is disabled, the polarity is controlled by
	the VGA registers.
	1	= Active high.
	0	= Active low.
3	HSYNC Polarity Control. When the LCD / TV timing generator is disabled, the polarity is controlled by
	the VGA registers.
	1	= Active high.
	0	= Active low.
2	BLANK# Polarity Control.
	1	= Active high.
	0	= Active low.
1	Dot Clock Source.
	1	= Dot Clock PLL Reference Source is External Pin = CLKIN
	0	= Dot Clock PLL Reference Source is the default PLL source.
	The CLKIN pin can be used an Interrupt for FP hot plug detection. When the pin is used as a clock, the
	interrupt signal is forced to the deassertion level.
	The CLKIN / Interrupt pin is always an input. It is never disabled. An internal pull up is active when the
	pin is configured as an Interrupt. When configured as a clock the internal pull up is disabled.
0	Lock Dot Clock PLL N/M Regs.
	1	= Dot Clock PLL N/M registers are locked. Use the LCD / TV PLL M/N registers and ignore the MSR
		register.
	0	= Dot Clock PLL N/M registers are writeable. The MSR register controls which PLL M/N registers are
		used
	When either supporting a TV Encoder or a Flat Panel, but not in VESA VGA mode, the LCD / TV PLL
	M/N registers must be set up for the proper Dot clock frequency. Then this bit is written with a 1 to lock
	the registers. When written with a 1, forces the Dot Clock PLL to only look at the LCD / TV PLL M/N
	registers.

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