Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

9.6.22.CR14Underline Location Register

I/O (and Memory Offset) Address:

 

3B5h/3D5h (index=14h)

 

 

Default:

 

 

 

 

 

 

 

0UUU UUUUb (U=Undefined)

 

 

Attributes:

 

 

 

 

 

 

Read/Write

 

 

7

 

 

 

6

5

4

0

 

 

 

Reserved

 

DWord

 

Count By

 

Underline Location

 

 

 

 

(0)

 

 

 

Mode

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

7

 

Reserved. Read as 0s.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

DWord Mode.

 

 

 

 

 

 

 

 

 

 

0

= Frame buffer addresses are interpreted by the frame buffer address decoder as being either byte

 

 

 

 

 

 

addresses or word addresses, depending on the setting of bit 6 of the CRT Mode Control Register

 

 

 

 

 

 

(CR17).

 

 

 

 

 

 

 

 

 

 

1

= Frame buffer addresses are interpreted by the frame buffer address decoder as being DWord

 

 

 

 

 

 

 

 

addresses, regardless of the setting of bit 6 of the CRT Mode Control Register (CR17).

 

 

 

 

 

 

Note that this bit is used in conjunction with bits 6 and 5 of the CRT Mode Control Register (CR17) to

 

 

 

 

select how frame buffer addresses from the processor are interpreted by the frame buffer address

 

 

 

 

 

 

decoder as shown below:

 

 

 

 

 

 

 

 

CR14[6]

CR17[6]

Addressing Mode

 

 

 

 

 

 

0

 

 

 

0

 

Word Mode

 

 

 

 

 

 

0

 

 

 

1

 

Byte Mode

 

 

 

 

 

 

1

 

 

 

0

 

DWord Mode

 

 

 

 

 

 

1

 

 

 

1

 

DWord Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

Count By 4.

 

 

 

 

 

 

 

 

 

 

0

= The memory address counter is incremented either every character clock or every other character

 

 

 

 

 

 

 

clock, depending upon the setting of bit 3 of the CRT Mode Control Register.

 

 

 

 

 

 

1

= The memory address counter is incremented either every 4 character clocks or every 2 character

 

 

 

 

 

 

 

clocks, depending upon the setting of bit 3 of the CRT Mode Control Register.

 

 

 

 

 

 

Note that this bit is used in conjunction with bit 3 of the CRT Mode Control Register (CR17) to select the

 

 

 

 

number of character clocks are required to cause the memory address counter to be incremented as

 

 

 

 

shown, below:

 

 

 

 

 

 

 

 

 

 

CR14[5]

CR17[3]

Address Incrementing Interval

 

 

 

 

 

 

0

 

 

 

0

 

every character clock

 

 

 

 

 

 

0

 

 

 

1

 

every 2 character clocks

 

 

 

 

 

 

1

 

 

 

0

 

every 4 character clocks

 

 

 

 

 

 

1

 

 

 

1

 

every 2 character clocks

 

 

 

 

 

 

 

4:0

 

Underline Location. This field specifies which horizontal line of pixels in a character box is to be used

 

 

 

 

to display a character underline in text mode. The horizontal lines of pixels in a character box are

 

 

 

 

 

 

numbered from top to bottom, with the top-most line being number 0. The value specified by these 5 bits

 

 

 

 

should be the number of the horizontal line on which the character underline mark is to be shown.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

125

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Image 125
Intel 815 manual 22. CR14Underline Location Register, CR146 CR176 Addressing Mode, Count By