Intel 815 manual 8. CR06Vertical Total Register, 9. CR07Overflow Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.6.8.CR06Vertical Total Register

I/O (and Memory Offset) Address:			3B5h/3D5h (index=06h)
Default:			00h
Attributes:			Read/Write (Group 0 Protection)
	Bit		Description
	7:0	Vertical Total Bits [7:0]. This field provides the 8 least significant bits of either a 10-bit or 12-bit value
		that specifies the total number of scan lines. This includes the scan lines both inside and outside of the
		active display area.
		In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical total is
		specified with a 10-bit value. The 8 least significant bits of this value are supplied by these 8 bits of this
		register, and the 2 most significant bits are supplied by bits 5 and 0 of the Overflow Register (CR07).
		In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical total is
		specified with a 12-bit value. The 8 least significant bits of this value are supplied by these 8 bits of this
		register, and the 4 most significant bits are supplied by bits [3:0] of the Extended Vertical Total Register
		(CR30).
		This 10-bit or 12-bit value should be programmed to equal the total number of scan lines, minus 2.

9.6.9.CR07Overflow Register

I/O (and Memory Offset) Address:						3B5h/3D5h (index=07h)
Default:						UU0U UUU0b (U=Undefined)
Attributes:						Read/Write (Group 0 Protection on bits [7:5, 3:0])
7				6	5	4	3	2	1	0
		Vert Sync		Vert Disp	Vert Total	Line Cmp	Vert Blnk	Vert Sync	Vert Disp	Vert Total
		Start Bit 9		En Bit 9	Bit 9	Bit 8	Start Bit 8	Start Bit 8	En Bit 8	Bit 8
		Bit					Description
	7		Vertical Sync Start Bit 9. The vertical sync start is a 10-bit or 12-bit value that specifies the beginning
			of the vertical sync pulse relative to the beginning of the active display area.
			In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical sync start
			is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
			Vertical Sync Start Register (CR10), and the most and second-most significant bits are supplied by this
			bit and bit 2, respectively, of this register.
			In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical display end is
			specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the
			Vertical Sync Start Register (CR10), and the 4 most significant bits are supplied by bits [3:0] of the
			Extended Vertical Sync Start Register (CR32) register. In extended modes, neither this bit, nor bit 2 of
			this register are used.
			This 10-bit or 12-bit value should be programmed to be equal to the number of scan lines from the
			beginning of the active display area to the start of the vertical sync pulse. Since the active display area
			always starts on the 0th scan line, this number should be equal to the number of the scan line on which
			the vertical sync pulse begins.

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