Intel 815 manual 20. CR12Vertical Display Enable End Register, CR13Offset Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

9.6.20.CR12Vertical Display Enable End Register

	I/O (and Memory Offset) Address:			3B5h/3D5h (index=12h)
	Default:			Undefined
	Attributes:			Read/Write
		Bit		Description
		7:0	Vertical Display Enable End Bits [7:0]. This register provides the 8 least significant bits of either a 10-
			bit or 12-bit value that specifies the number of the last scan line within the active display area.
			In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, this value is
			described in 10 bits with bits [6,1] of the Overflow Register (CR07) supplying the 2 most significant bits.
			In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, this value is described in
			12 bits with bits [3:0] of the Extended Vertical Display Enable End Register (CR31) supplying the 4 most
			significant bits.
			This 10-bit or 12-bit value should be programmed to be equal to the number of the last scan line within
			in the active display area. Since the active display area always starts on the 0th scan line, this number
			should be equal to the total number of scan lines within the active display area, minus 1.
9.6.21.	CR13Offset Register
	I/O (and Memory Offset) Address:			3B5h/3D5h (index=13h)
	Default:			Undefined
	Attributes:			Read/Write

In High Resolution modes the Start Addresses in CR0C, CR0D, CR40, and CR42 must be programmed before CR13. This is not a requirement in VGA mode.

Bit	Description
7:0	Offset Bits [7:0] of a 12-bit value. This register provides the 8 least significant bits of a 12-bit value
	that specifies the number of words or Dwords of frame buffer memory occupied by each horizontal row
	of characters. Whether this value is interpreted as the number of words or Dwords is determined by the
	settings of the bits in the Clocking Mode Register (SR01.) This 12-bit value should be programmed to be
	equal to either the number of words or Dwords (depending on the setting of the SR01 register) of frame
	buffer memory that is occupied by each horizontal row of characters.
	The companion extended offset register CR41[3:0] specifies the 4 most significant bits of the 12-bit
	value.
	It is required of software to write both CR41[3:0] and CR13[7:0] to the desired 12-bit offset value for
	correct hardware operation. Where an 8-bit value is desired, for example in standard VGA mode,
	software must write “0000” to CR41[3:0], and the desired 8-bit value to CR13[7:0].
	Note that unlike the operation of the other CRTC extension registers, CR80[0] – CRT Controller
	Interpretation Enable bit has no effect on CR41 and CR13.

124