Intel 815 DPLYSTAS-Display Status Select Register, Reserved Flat Panel Hot Plug Detect Enable

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

20.3.5.DPLYSTAS—Display Status Select Register

Memory Offset Address:	70024h
Default:	0000h
Attributes:	Read/Write

This register selects the proper events to be signaled to the Interrupt Control Register in the command stream. Status bits 0 and 1 are logically ORed to become the Vertical Blank status bit and status bits 8, 9, and 10 are logically ORed to become the Display Event status bit. These 2 sets of status bits are on separate bytes for future expansion purposes. The architecture allows each byte to be logically ORed. The enables, for each status bit is in the corresponding bit or the upper word. If a status enable bit is asserted, then the corresponding status bit is considered in the interrupt generation. The Status bits capture the event if enabled and are cleared by writing a 1 to the bit. This register has separate byte enables for writing.

31						27	26	25	24
					Reserved		FP Hot	VSYNC	Vert Line
							Plug	En	Comp En
							Enable
23							18	17	16
					Reserved			Verit Blank	OVL Reg
								En	Upd En
		15		14		11	10	9	8
	FP Hot				Reserved		FP Hot	VSYNC	Vert Line
	Plug Status						Plug		Comp
							Interrupt
7							2	1	0
					Reserved			Verit Blnk	OVL Reg
								Dply Event	Upd Vblnk
								Sel	Sel
	Bit					Descriptions
31:27			Reserved.
26			Flat Panel Hot Plug Detect Enable.
			0	= Flat Panel Hot Plug Detect Disabled
			1	= Flat Panel Hot Plug Detect Enabled
25			Vertical Sync Status Enable.
			0	= Vertical Sync Status Disabled
			1	= Vertical Sync Status Enabled
24			Display Line Compare Enable.
			0	= Display Line Compare Status Disabled
			1	= Display Line Compare Status Enabled

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