Intel 815 manual Bit Description, Ram

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Bit	Description
7:6	Graphics Mode Select (GMS). This field is used to enable/disable the Internal Graphics device and
	select the amount of Main Memory that is “Stolen” to support the Internal Graphics device in VGA
	(non-linear) mode only. These 2 bits only have meaning if we are not in AGP mode.
	00 = Internal Graphics Device Disabled, No memory “Stolen”
	01 = Internal Graphics Device Enabled, No memory “Stolen”
	10 = Internal Graphics Device Enabled, 512K of memory “Stolen” for frame buffer.
	11 = Internal Graphics Device Enabled, 1M of memory “Stolen” for frame buffer.
	Note:
	When the Internal Graphics Device is Disabled (00) the Graphics Device and all of its memory and
	I/O functions are disabled and the clocks to this logic are turned off, memory accesses to the VGA
	range (A0000-BFFFF) will be forwarded on to the hub interface, and the Graphics Local Memory
	space is NOT “stolen” from main memory. Any change to the SMRAM register will not affect AGP
	mode or cause the controller to go into AGP mode. When this field is non-0 the Internal Graphics
	Device and all of its memory and I/O functions are enabled, all non-SMM memory accesses to the
	VGA range will be handled internally and the selected amount of Graphics Local Memory space (0,
	512K or 1M) is “stolen” from the main memory. Graphics Memory is “stolen” AFTER TSEG Memory
	is “stolen”.
	Once D_LCK is set, these bits becomes read only.
	GMCH does not support VGA on local memory. Software must not use the 01 mode for VGA
5:4	Upper SMM Select (USMM). This field is used to enable/disable the various SMM memory ranges
	above 1 MB. TSEG is a block of memory (“Stolen” from Main Memory at [TOM-Size] : [TOM]) that is
	only accessable by the processor and only while operating in SMM mode. HSEG is a Remap of the
	AB segment at FEEA0000 : FEEBFFFF. Both of these areas, when enabled, are usable as SMM
	RAM.
	00 = TSEG and HSEG are both Disabled
	01 = TSEG is Disabled, HSEG is Conditionally Enabled
	10 = TSEG is Enabled as 512 KB and HSEG is Conditionally Enabled
	11 = TSEG is Enabled as 1 MB and HSEG is Conditionally Enabled
	Note:
	Non-SMM Operations (SMM processor accesses and all other access) that use these address
	ranges are forwarded to the hub interface.
	Once D_LCK is set, these bits becomes read only.
	HSEG is ONLY enabled if LSMM = 00.
3:2	Lower SMM Select (LSMM). This field controls the definition of the A&B segment SMM space
	00 = AB segment Disabled (no one can write to it).
	01 = AB segment Enabled as General System RAM (anyone can write to it).
	10 = AB segment Enabled as SMM Code RAM Shadow. Only SMM Code Reads can access DRAM
	in the AB segment (processor code reads only). SMM Data operations and all Non-SMM
	Operations go to either the internal graphics device or are broadcast on the hub interface.
	11 = AB segment Enabled as SMM RAM. All SMM operations to the AB segment are serviced by
	DRAM, all Non-SMM Operations go to either the internal Graphics Device or are broadcast on
	the hub interface (processor SMM R/W can access SMM space).
	When D_LCK is set bit 3 becomes Read Only, and bit 2 is Writable ONLY if bit 3 is a “1”. When bit 3
	is set only the processor can access it.

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