Intel 815 manual ABBEND-Active Batch Buffer End Address Register debug

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

16.1.15. ABB_END—Active Batch Buffer End Address Register (debug)

Address Offset:	020D0h
Default Value:	00000000h
Access:	Read Only
Size:	32 bits

This register is loaded with the end address of the Batch Buffer request. The ABB_STR and ABB_END Registers will not get loaded if they are popped off of the stack. This can occur if a low priority ring batch buffer is interrupted at a chain point by Interrupt Priority ring execution and then is later continued. The Start and End addresses for the low priority ring chain portion that was interrupted will not be stored in the ABB_STR and ABB_END Registers. This is an operational anomaly that will not be corrected.

31	26	25	3	2	1	0
	Reserved		Batch Buffer Request End Address	Reserved		Source of the
						Batch buffer
Bit			Description
31:26	Reserved
25:3	Batch Buffer Request End Address
2	Reserved
1:0	Source of the Batch Buffer
	00 = Low Priority Ring
	01 = Interrrupt Ring
	1X = Reserved

16.1.16. DMA_FADD—DMA Engine Fetch Address (debug)

Address Offset:	020D4h
Default Value:	00000000h
Access:	Read Only
Size:	32 bits

This register contains the offset from the start address of the instruction being fetched by the DMA engine.

31		26	25	3	2	1	0
	Reserved			Current Address of the DMA Pointer	Reserved	User of DMA Eng
Bit				Description
31:26	Reserved.
25:3	Current DMA Address.
2	Reserved
1:0	User of the DMA Engine.
	00	= Low Priority Ring
	01	= Interrupt Ring
	10	= Batch Buffer from Low Priority Ring
	11	= Batch Buffer from Interrupt Ring

318