Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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10.4.3.Instruction Parser

The following figure shows a high-level diagram of the GC instruction interface. The GC's Instruction Parser (IP) unit is responsible for:

Detecting the presence of instructions (within the Ring Buffers)

Arbitrating the execution of instruction streams

Reading instructions from Ring Buffers and Batch Buffers via DMA

Parsing the common "Client" (destination) field of instructions

Execution of Instruction Parser instructions (which control IP functionality, provide synchronization functions as well as provide miscellaneous GC control functions)

Redirection of 2D and 3D instructions to the appropriate destination while following drawing engine concurrency and coherency rules

Figure 26. Graphics Controller Instruction Interface

Low Priority Ring

(Graphics Memory)

Batch Buffers

Instruction

 

 

Batch Buff Instr

 

 

Instruction

DMA

 

Interrupt Ring

 

 

(Graphics Memory)

Batch Buffers

Instruction

 

Instruction access and decoding

2D Instructions

BLT

Engine

DMA

Instr

FIFO

Parser

3D Instructions (3D state,

3D Primitives, STRBLT,

Motion Compensation) 3D

DMA

Batch Buff Instr

Instruction

Instruction Parser Instructions

- Parser Control

(e.g., Batch Buffer Instr., NOP,

Sync ID, Flush, breakpoint )

Engine

Display

- Memory Interface Control Engine (e.g., Store DWord to memory)

- Display/Overlay Control

 

(e.g., Front Buffer, Scan

Overlay

Lines, Overlay Flip

Engine

 

cmd_str.vsd

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Intel 815 manual Instruction Parser, Interrupt Ring