Intel 815 manual 36. CR41Extended Offset Register, 37. CR42Extended Start Address High Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.6.36.CR41Extended Offset Register

I/O (and Memory Offset) Address:				3B5h/3D5h (index=41h)
Default:				00h
Attributes:				Read/Write
7				4	3		0
			Reserved (0000)			Offset Bits 11:8
		Bit			Description
	7:4		Reserved. Read as 0’s. This field must be 0’s when this register is written.
	3:0		Offset Bits [11:8] of a 12-bit value. This register provides the 4 most significant bits of a 12-bit value
			that specifies the number of words or Dwords of frame buffer memory occupied by each horizontal row
			of characters. Whether this value is interpreted as the number of words or Dwords is determined by the
			settings of the bits in the Clocking Mode Register (SR01.) This 12-bit value should be programmed to be
			equal to either the number of words or Dwords (depending on the setting of the SR01 register) of frame
			buffer memory that is occupied by each horizontal row of characters.
			The companion offset register CR13[7:0] specifies the 8 least significant bits of the 12-bit value.
			It is required of software to write both CR41[3:0] and CR13[7:0] to the desired 12-bit offset value for
			correct hardware operation. Where an 8-bit value is desired, for example in standard VGA mode,
			software must write “0000” to CR41[3:0], and the desired 8-bit value to CR13[7:0].
			Note that unlike the operation of the other CRTC extension registers, CR80[0] – CRT Controller
			Interpretation Enable bit has no effect on CR41 and CR13.

9.6.37.CR42Extended Start Address High Register

I/O (and Memory Offset) Address:			3B5h/3D5h (index=42h)
Default:			00h
Attributes:			Read/Write
	Bit		Description
	7:0	Start Address High Bits [31:24]. This register provides bits [31:24] of a 32-bit buffer address that the
		data to be shown in the active display area begins. (default is 0)
		In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the start address is
		specified with a 16-bit value. The eight bits of the Start Address High Register (CR0C) provide the eight
		most significant bits of this value, while the eight bits of the CR0D register provide the eight least
		significant bits.
		In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the start address is
		specified with a 32-bit value. Bits [31:24] of this value are provided by this register. Bits [23:18] of this
		value are provided by bits [5:0] of the Extended Start Address Register (CR40). Bits [17:10] of this value
		are provided by the Start Address High Register (CR0C). Bits [9:2] of this value are provided by the
		Start Address Low Register (CR0D). Bits [1:0] of this value are always 0, and therefore not provided. It
		should be further noted that, in extended modes, the 30 bits from these four registers are double-
		buffered and synchronized to VSYNC to ensure that changes occurring on the screen as a result of
		changes in the start address always have a smooth or instantaneous appearance. To change the start
		address in extended modes, all four registers must be set for the new value, and then bit 7 of the
		Extended Start Address Register (CR40) must be set to 1. Only then will the graphics controller update
		the start address on the next VSYNC. When the update is done, the graphics controller sets bit 7 of the
		Extended Start Address Register (CR40) back to 0.

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