Intel 815 manual Register/Instruction Category, Comment

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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Table 16.		Overlay Register/Instruction Categories
		Register/Instruction Category	Mem. Address Offset			Comment
	Overlay 0 Register Update Address		30000h	•	Used to update Overlay 0 registers.
	(OV0ADD)			•	Provides physical memory address of
					buffer area used for updating on-chip
					registers
				•	Write of OV0ADD register causes
					hardware to update on-chip registers on
					next VBLANK.
	Display/Overlay 0 Status Register		30008h	•	Overlay Status bits
	(DOV0STA)
	Gamma Correction (GAMMA[0:5])		30010h–30027h	•	Not part of double-buffer scheme. Access
					registers directly.
	Overlay Register Sets		301xxh	•	“xx” indicates a particular register address.
	•	Overlay Buffer Pointer	(on chip RO regs)	•	On-chip registers are not directly writeable.
	•	Overlay Stride				Registers are double buffered
			Base+xxh			(buffer in memory and on-chip
	•	Overlay Initial Phase				registers).
			(Mem Buffer regs)
						Software sets up buffer in
	•	Overlay Dest. Window Position/Size
						memory.
	• Overlay Source Size
						Software writes to OV0ADD
	•	Overlay Scale Factor				Register which provides memory buffer
						address location and causes hardware
	•	Overlay Color Correction				to read memory buffer and update on-
	•	Overlay Destination Color Key				chip registers during next VBLANK.
				•	On-chip registers can be read through
	•	Overlay Source Color Key
					Debug read path. See OV0ADD register
	•	Overlay Configuration			description
	•	Overlay Command
	Overlay Flip Instruction		NA	•	This instruction invokes the Overlay
					register update.

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