Intel 815 manual 9. GR07Color Don’t Care Register, 10. GR08Bit Mask Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.3.9.GR07Color Don’t Care Register

I/O (and Memory Offset) Address:			3CFh (Index=07h)
Default:			0Uh (U=Undefined)
Attributes:			Read/Write
7			4	3	2	1	0
		Reserved (0000)		Ignore	Ignore	Ignore	Ignore
				Color	Color	Color	Color
				Plane 3	Plane 2	Plane 1	Plane 0
	Bit			Description
7:4		Reserved. Read as 0s.
3:0		Ignore Color Plane [3:0]. Note that these bits have effect only when bit 3 of the Graphics Mode
		Register (GR05) is set to 1 to select read mode 1.

0 = The corresponding bit in the Color Compare Register (GR02) is not used in color comparisons.

1 = The corresponding bit in the Color Compare Register (GR02) is used in color comparisons.

9.3.10.GR08Bit Mask Register

I/O (and Memory Offset) Address: 3CFh (Index=08h)

Default:			Undefined
Attributes:			Read/Write
	Bit		Description
	7:0	Bit Mask.
		0 = The corresponding bit in each of the 4 memory planes is written to with the corresponding bit in the
			memory read latches.
		1 = Manipulation of the corresponding bit in each of the 4 memory planes via other mechanisms is
			enabled.
		Notes:
		1.	This bit mask applies to any writes to the addressed byte of any or all of the 4 memory planes,
			simultaneously.
		2.	This bit mask is applicable to any data written into the frame buffer by the processor, including data
			that is also subject to rotation, logical functions (AND, OR, XOR), and Set/Reset. To perform a
			proper read-modify-write cycle into frame buffer, each byte must first be read from the frame buffer
			by the processor (and this will cause it to be stored in the memory read latches). The Bit Mask
			Register must be set, and the new data then must be written into the frame buffer by the processor.

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