Intel 815 manual 332

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Bit		Description
31:28	Overlay Delay Timer1. Is used to insert waits states in between sets of YUVY requests to MM. The
	value in this register is multiplied by 16 to determine the wait state clock count.
27:24	Overlay Delay Timer0. Is used to insert waits states in between any two overlay streamer requests to
	MM except between sets of YUVY. The value in this register is multiplied by 16 to determine the wait
	state clock count.
23	Reserved
22:20	MM Display Burst Length. Size in QWs of individual requests issued to Memory. Use Multiples of 16
	QWs for tiled memory.
	000	= 8 Qws (N/A if Trickle Feed is on)
	001	= 16 Qws,
	010	= 24 Qws
	011	= 32 Qws
	100	= 40 Qws
	101	= 48 Qws
	110	= 56 Qws
	111	= 64 QWs
19:18	Reserved
17:12	MM Display FIFO Watermark. Number of QWs stored in FIFOs, below which the DSI will generate
	requests to LMI (Value has to less than 32 and should be as recommended in the high priority
	bandwidth analysis spreadsheet).
11	Reserved
10:8	LM Display Burst Length (Reserved in Intel® 815 chipset). Size in QWs of individual requests
	issued to Memory. Use Multiples of 16 QWs for tiled memory.
	000	= 8 QWs (N/A if Trickle Feed is on)
	001	= 16 QWs
	010	= 24 QWs
	011	= 32 QWs
	100	= 40 QWs
	101	= 48 QWs
	110	= 56 QWs
	111	= 64 QWs.
7:6	Overlay Watermark. Number of QWs stored in the overlay FIFO below which a new overlay request
	will be generated.
	00 = 24 QWs (default)
	01 = 20 QWs
	10 = 16 QWs
	11 = 12 QWs
5:0	LM Display FIFO Watermark (Reserved in Intel® 815 chipset). Number of QWs stored in FIFOs,
	below which the DSI will generate requests to LMI (Value has to less than 32 and should be as
	recommended in the high priority bandwidth analysis spreadsheet).

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