Intel 815 2. AR000FPalette Registers 0F, 3. AR10Mode Control Register, Pixel Width/Clock Select

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.4.2.AR[00:0F]Palette Registers [0:F]

I/O (and Memory Offset) Address:				Read at 3C1h and Write at 3C0h; (index=00h-0Fh)
Default:				00UU UUUUb (U=Undefined)
Attributes:				Read/Write
7		6	5	0
		Reserved		Palette Bits P[5:0]
	Bit			Description
7:6		Reserved. Read as 0s.
5:0		Palette Bits P[5:0]. In each of these 16 registers, these are the lower 6 of 8 bits that are used to map
		either text attributes or pixel color input values (for modes that use 16 colors) to the 256 possible colors
		available to be selected in the palette.

Note:

Bits 3 and 2 of the Color Select Register (AR14) supply bits P7 and P6 for the values contained in all 16 of these registers. Bits 1 and 0 of the Color Select Register (AR14) can also replace bits P5 and P4 for the values contained in all 16 of these registers, if bit 7 of the Mode Control Register (AR10) is set to 1.

9.4.3.AR10Mode Control Register

I/O (and Memory Offset) Address:						Read at 3C1h and Write at 3C0h; (index=10h)
Default:						UUh (U=Undefined)
Attributes:						Read/Write
7				6	5	4	3		2	1	0
		Palette		Pixel	Pixel	Reserved		Enable	Enable	Select	Graphics/
		Bits P5,		Width/Clk	Panning	(0)		Blink/	Line	Display	Alpha
		P4 Select		Select	Compat			Select	Graphics	Type	Mode
								Bkgnd Int	Char Code
		Bit					Description
	7		Palette Bits P5, P4 Select.
			0 = P5 and P4 for each of the 16 selected colors (for modes that use 16 colors) are individually
				provided by bits 5 and 4 of their corresponding Palette Registers (AR[00:0F]).
			1 = P5 and P4 for all 16 of the selected colors (for modes that use 16 colors) are provided by bits 1 and
				0 of Color Select Register (AR14).
	6		Pixel Width/Clock Select.
			0 = Six bits of video data (translated from 4 bits via the palette) are output every dot clock.
			1 = Two sets of 4 bits of data are assembled to generate 8 bits of video data which is output every
				other dot clock, and the Palette Registers (AR[00:0F]) are bypassed.
			Note:
			This bit is set to 0 for all of the standard VGA modes, except mode 13h.

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