Intel 815 manual Instruction Parser Instructions, Introduction, Instruction Descriptions

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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11.Instruction Parser Instructions

11.1.Introduction

The Graphics Controller (GC) contains an extensive set of instruction for controlling 2D and 3D operations. This section describes the programmer’s interface to these instructions. The instructions can be categorized as follows:

•3D Instructions. The 3D pipeline states and processing functions are controlled by a set of 3D instructions. (See the 3D Instruction section for detailed instruction descriptions).

•2D Instructions. The 2D instructions are used to invoke BLT operations. (See the 2D Register and instruction section for detailed instruction descriptions).

•Instruction Parser Instructions. These instructions control various GC interface units (eg. Local Memory Interface, Display Interface), setting break points, etc.

11.2.Instruction Descriptions

11.2.1.GFXCMDPARSER_NOP_IDENTIFICATION

This instruction effectively provides a "no-operation" instruction that can be used to pad the instruction stream (e.g., in order to pad out a batch buffer to a QWord boundary). However, there is one operation this instruction can perform. If the Enable bit is set, the command parser will write the Identification Number field contents into the NOP Identification Register. This provides a general-purpose instruction stream tagging ("breadcrumb") mechanism.

One possible use would be for software to use a NOP_IDENTIFICATION instruction to tag a subsequent Breakpoint Interrupt event. The GFXCMDPARSER_NOP_IDENTIFICATION instruction format is:

DWord	Bit		Description
0	31:29	Client: 000 – Instruction Parser
	28:23	Opcode: 00h
	22	Enable:
		1	= write the identification number.
		0	= don’t write the identification number.
	21:6	Identification Number.
	5:0	Reserved. MBZ

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