Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

16.2.4.IMR—Interrupt Mask Register

Address Offset:

020A8h

Default Value:

FFFFh

Access:

Read/Write

Size:

16 bits

An interrupt that is masked by this register will not appear in the Interrupt Identity Register and will not generate an interrupt.

15

 

 

14

13

12

11

10

9

8

 

 

HW

 

Reserved

Sync

Pri Dply

Reserved

Overlay 0

Reserved

 

 

Detect

 

 

 

Status

Flip

 

Flip

 

 

 

Error

 

 

 

Toggle

Pending

 

Pending

 

 

 

Master

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

6

5

4

3

2

1

0

 

 

Pri Dply

Pri Dply

Reserved

Reserved

Reserved

Reserved

User

Breakpoint

 

 

VBLANK.

Event

 

 

 

 

Defined

 

 

 

 

 

 

 

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

15:0

 

Interrupt Mask Bits. See. Table 17

 

 

 

 

 

 

 

 

0 = Not Masked

 

 

 

 

 

 

 

 

 

 

1 = Masked

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

325

Page 325
Image 325
Intel 815 manual IMR-Interrupt Mask Register, Interrupt Mask Bits. See. Table