Intel 815 manual Instpm

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Table 2.	Memory-Mapped Registers
	Address Offset		Symbol		Register Name	Access
	020C0h		INSTPM		Instruction Parser Mode Register	R/W
	020C1h–020C3h				Reserved	
	020C4h–020C7h		INSTPS		Instruction Parser State Register	RO
	020C8h–020CBh		BBP_PTR		Batch Buffer Parser Pointer Register	RO
	020CCh–020CFh		ABB_SRT		Active Batch Buffer Start Address Register	RO
	020D0h–020D3h		ABB_END		Active Batch Buffer End Address Register	RO
	020D4h–020D7h		DMA_FADD		DMA Engine Fetch Address Register	RO
	020D8h–020DBh		FW_BLC		FIFO Watermark and Burst Length Control	R/W
	020DCh–020DBh				Reserved	
	020DCh–020DFh		MEM_MODE		Memory Interface Mode Register	R/W
	020E0h−02FFFh				Reserved	
			Memory Control Registers (03000h−03FFFh)
	03000h		DRT		DRAM Row Type	R/W
	03001h		DRAMCL		DRAM Control Low	R/W
	03002h		DRAMCH		DRAM Control High	R/W
	03003h−03FFFh				Reserved	
				Reserved (04000h−04FFFh)
	04000h−04FFFh				Reserved	
			I/O Control Registers (05000h−05FFFh)
	05000h−05003h		HVSYNC		HSYNC/VSYNC Control	R/W
	05010h−05013h		GPIOA		General Purpose I/O Control A	R/W
	05014h−05017h		GPIOB		General Purpose I/O Control B	R/W
	05018h−05FFFh				Reserved	
		Clock Control and Power Management Registers (06000h−06FFFh)
	06000h−06003h		DCLK_0D		Display Clock 0 Divisor	R/W
	06004h−06007h		DCLK_1D		Display Clock 1 Divisor	R/W
	06008h−0600Bh		DCLK_2D		Display Clock 2 Divisor	R/W
	0600Ch−0600Fh		LCD_CLKD		LCD Clock Divisor	R/W
	06010h−06013h		DCLK_0DS		Display and LCD Clock Divisor Select	R/W
	06014h−06017h		PWR_CLKC		Power Management and Miscellaneous Clock	R/W
					Control
				Reserved (07000h−0FFFFh)
	07000h−0FFFFh				Reserved	
			Graphics Translation Table Range Definition (10000h−1FFFFh)
	10000h−1FFFFh		GTT		Graphics Translation Table Range Definition	WO
				Reserved (20000h−2FFFFh)
	20000h−2FFFFh				Reserved	

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