Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

9.2.3.SR01Clocking Mode

I/O (and Memory Offset) Address:

3C5h (Index=01h)

 

 

 

 

Default:

 

 

 

 

00h

 

 

 

 

 

 

 

Attributes:

 

Read/Write

 

 

 

 

7

6

 

5

4

3

 

2

1

0

 

 

 

 

Reserved (00)

 

Screen Off

Shift 4

 

Dot Clock

 

Shift Load

Reserved

8/9 Dot

 

 

 

 

 

 

 

 

 

 

Divide

 

 

(0)

Clocks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

 

 

 

Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7:6

 

Reserved. Read as 0s.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

Screen Off. The display and hardware cursor will be disabled by setting the Screen Off bit. However,

 

 

 

 

 

the Overlay stream will continue to be displayed so it must be halted separately if you want to blank the

 

 

 

 

 

screen.

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = Normal Operation (default).

 

 

 

 

 

 

 

 

 

 

 

 

1 = Disables video output (blanks the screen) and turns off the picture-generating logic. This allows the

 

 

 

 

 

full memory bandwidth to be available for processor accesses. Synchronization pulses to the

 

 

 

 

 

display, however, are maintained. Setting this bit to 1 can be used as a way to more rapidly update

 

 

 

 

 

the frame buffer.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

Shift 4.

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = Load video shift registers every 1 or 2 character clocks (depending on bit 2 of this register) (default).

 

 

 

 

 

1 = Load shift registers every 4th character clock.

 

 

 

 

 

 

 

 

 

 

3

 

Dot Clock Divide. Setting this bit to 1 divides the dot clock by two and stretches all timing periods. This

 

 

 

 

 

bit is used in standard VGA 40-column text modes to stretch timings to create horizontal resolutions of

 

 

 

 

 

either 320 or 360 pixels (as opposed to 640 or 720 pixels, normally used in standard VGA 80-column

 

 

 

 

 

text modes).

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = Sequencer master clock output on the PCLK pin (used for 640 (720) pixel modes); Pixel clock is left

 

 

 

 

 

unaltered (default).

 

 

 

 

 

 

 

 

 

 

 

 

1 = Pixel clock divided by 2 output on the PCLK pin (used for 320 (360) pixel modes).

 

 

 

 

 

 

 

 

 

 

2

 

Shift Load. Bit 4 of this register must be 0 for this bit to be effective.

 

 

 

 

 

 

 

0 = Load video data shift registers every character clock (default).

 

 

 

 

 

 

 

1 = Load video data shift registers every other character clock.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

Reserved. Read as 0s.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

8/9 Dot Clocks. This bit determines whether a character clock is 8 or 9 dot clocks long.

 

 

 

 

 

 

0 = 9 dot clocks (9 horizontal pixels) per character in text modes with a horizontal resolution of 720

 

 

 

 

 

pixels (default).

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = 8 dot clocks (8 horizontal pixels) per character in text modes with a horizontal resolution of 640

 

 

 

 

 

pixels.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Image 86
Intel 815 manual 3. SR01Clocking Mode, Shift