Intel 815 19. I/O Control Registers, HVSYNC-HSYNC/VSYNC Control Register, HSYNC/VSYNC Control1916

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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19.I/O Control Registers

19.1.HVSYNC—HSYNC/VSYNC Control Register

Address Offset:				05000h
Default Value:				00000000h
Size:				32 bits
Attribute:				R/W
Bits 19:16 are for DPMS and DDC Sync Select.
			DPMS MODE	HSYNC/VSYNC Control[19:16]
	Power On			0000 (i.e., pulse H and V)
	StandBye			0010 (i.e., pulse V)
	Suspend			1000 (i.e., pulse H)
	Power Off			1010 (no pulse on H & V)
31				20	19		18	17	16
			Reserved			VSYNC	VSYNC	HSYNC	HSYNC
						Control	Data	Control	Data
15								1	0
				Reserved					HSYNC/
									VSYNC
									En
		Bit			Description
	31:20		Reserved.
	19		VSYNC Control. Bit 19 (VSYNC Control) and bit 18 (VSYNC Data) are used by BIOS to take over the
			sync during DDC1 communication during POST. The BIOS can force the VSYNC data at the same time
			as VSYNC control enables this signal as an output, so that the VSYNC pulse occurs on every write by
			the BIOS. This is done to speed up some very slow DDC communications.
			0 = Normal VSYNC output
			1 = Contents of VSYNC Data will go out to VSYNC pin.
	18		VSYNC Data
	17		HSYNC Control
			0 = Normal HSYNC output
			1 = Contents of HSYNC Data will go out to HSYNC pin.
	16		HSYNC Data.
	15:1		Reserved.
	0		HSYNC/VSYNC Enable.
			0 = HSync and VSync are deactivated when the internal DAC is disabled. (default)
			1 = HSync and VSync remain active when the internal DAC is disabled via the PWR_CLKC register.

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