Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

 

 

 

 

 

 

 

 

R

 

13.9. GFXRENDERSTATE_MAP_LOD_LIMITS

224

 

13.10. GFXRENDERSTATE_MAP_LOD_CONTROL

225

 

13.11. GFXRENDERSTATE_MAP_PALETTE_LOAD

226

 

13.12. GFXRENDERSTATE_MAP_COLOR_BLEND_STAGES

227

 

13.13. GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES

230

 

13.14. GFXRENDERSTATE_COLOR_FACTOR

232

 

13.15. GFXRENDERSTATE_COLOR_CHROMA_KEY

233

 

13.16. GFXRENDERSTATE_SRC_DST_BLEND_MONO

235

 

13.17. GFXRENDERSTATE_Z_BIAS_ALPHA_FUNC_REF

238

 

13.18. GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_ MODE

239

 

13.19. GFXRENDERSTATE_BOOLEAN_ENA_1

241

 

13.20. GFXRENDERSTATE_BOOLEAN_ENA_2

242

 

13.21. GFXRENDERSTATE_FOG_COLOR

243

 

13.22. GFXRENDERSTATE_DRAWING_RECTANGLE_INFO

243

 

13.23. GFXRENDERSTATE_SCISSOR_ENABLE

245

 

13.24. GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO

246

 

13.25.

Stipple Pattern

......................................................................................................

247

 

13.26. GFXRENDERSTATE_ANTI_ALIASING

248

 

13.27. GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION_RULE

249

 

13.28. GFXRENDERSTATE_DEST_BUFFER_VARIABLES

251

 

13.29.

Programming Hints/Rules

253

14.

Clock Control Registers

257

 

14.1.

Programming Notes

257

 

14.2. DCLK_0D—Display Clock 0 Divisor Register

258

 

14.3. DCLK_1D—Display Clock 1 Divisor Register

259

 

14.4. DCLK_2D—Display Clock 2 Divisor Register

260

 

14.5. LCD_CLKD—LCD Clock Divisor Register

261

 

14.6. DCLK_0DS—Display & LCD Clock Divisor Select Register

262

 

14.7. PWR_CLKC—Power Management and Miscellaneous Clock Control

264

15.

Overlay Registers

265

 

15.1. OV0ADD—Overlay 0 Register Update Address Register

267

 

15.2.

DOV0STA—Display/Overlay 0 Status Register

268

 

15.3.

Gamma Correction

......................................................................................................

269

 

 

 

15.3.1.1.

GAMC[5:0]—Gamma Correction Registers

269

 

 

 

15.3.1.2. Mathematical Gamma Correction For Overlay

271

 

15.4.

Memory Offset Registers

274

 

 

15.4.1.

Overlay Buffer Pointer Registers

274

 

 

 

15.4.1.1. OBUF_0Y—Overlay Buffer 0 Y Pointer Register

274

 

 

 

15.4.1.2. OBUF_1Y—Overlay Buffer 1 Y Pointer Register

275

 

 

 

15.4.1.3. OBUF_0U—Overlay Buffer 0 U Pointer Register

275

 

 

 

15.4.1.4. OBUF_0V—Overlay Buffer 0 V Pointer Register

276

 

 

 

15.4.1.5. OBUF_1U—Overlay Buffer 1 U Pointer Register

276

 

 

 

15.4.1.6. OBUF_1V—Overlay Buffer 1 V Pointer Register

277

 

 

15.4.2.

Overlay Stride Registers

277

 

 

 

15.4.2.1. OV0STRIDE—Overlay 0 Stride Register

277

 

 

15.4.3.

Overlay Initial Phase Registers

278

 

 

 

15.4.3.1. YRGB_VPH—Y/RGB Vertical Phase Register

278

 

 

 

15.4.3.2.

UV_VPH—UV Vertical Phase Register

279

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Intel 815 manual Gfxrenderstatemaplodlimits