6. AR13Horizontal Pixel Panning Register, Reserved | Intel 815

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

9.4.6.AR13Horizontal Pixel Panning Register

I/O (and Memory Offset) Address:					Read at 3C1h and Write at 3C0h; (index=13h)
Default:					0Uh (U=Undefined)
Attributes:					Read/Write
7					4	3	0
				Reserved (0000)			Horizontal Pixel Shift


		Bit				Description

	7:4		Reserved.

	3:0		Horizontal Pixel Shift 3-0.This field holds a 4-bit value that selects the number of pixels by which the
			image is shifted horizontally to the left. This function is available in both text and graphics modes.
			In text modes with a 9-pixel wide character box, the image can be shifted up to 9 pixels to the left. In text
			modes with an 8-pixel wide character box, and in graphics modes other than those with 256 colors, the
			image can be shifted u0p to 8 pixels to the left.
			In standard VGA mode 13h (where bit 6 of the Mode Control Register, AR10, is set to 1 to support 256
			colors), bit 0 of this register must remain set to 0, and the image may be shifted up to only 4 pixels to
			the left. In this mode, the number of pixels by which the image is shifted can be further controlled using
			bits 6 and 5 of the Preset Row Scan Register (CR08).
			Number of Pixels Shifted
					8-Pixel Text		256-Color
			Bits [3:0]	9 Pixel Text	& Graphics		Graphics
			0h	1	0		0
			1h	2	1		Undefined
			2h	3	2		1
			3h	4	3		Undefined
			4h	5	4		2
			5h	6	5		Undefined
			6h	7	6		3
			7h	8	7		Undefined
			8h	0	Undefined		Undefined

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Image 105

Intel 815 manual 6. AR13Horizontal Pixel Panning Register, Reserved, Pixel Text Color, Pixel Text Graphics

Contents

Programmer’s Reference Manual PRM Intel 815 Chipset Graphics Controller Intel 815 Chipset Graphics Controller PRM, Rev Contents 100 106 141 Monosrccopyimmediateblt Gfxrenderstatemaplodlimits 15.4.3.3 HORZPH-Horizontal Phase Register 279 15.4.3.4 16.2.5 Figures Tables Revision History RevDate This page is intentionally left blank Introduction TerminologyTerm Description MCH Reference Documents Intel 815 Chipset Overview Intel 82815 Chipset Gmch Overview I/O Controller Hub Host Interface Intel 82815 Chipset Gmch Block Diagram Data Rate Signaling Level System Memory InterfaceMultiplexed AGP and Display Cache Interface Intel 82815 Chipset Gmch Integrated Graphics Support Hub Interface Three PCI Devices on Gmch Gmch Power DeliverySystem Clocking Front Side Bus System Memory Display Cache Interface Multi-Mode Capability Requirements Supported Single Monitor and Multi-monitor Configurations Configuration Single Monitor Multi-monitor System Startup Device Mode Auto-Detect Flowchart Software Start-Up Sequence Graphics Driver Startup Switching Device modes System Memory Space System Address Map Graphics Controller Register Memory and I/O Map Memory and I/O Space Registers Reserved 50000h−5FFFFh. Reserved in the Intel 815 chipset GC Register Memory Address Map Address Offset Symbol Register Name AccessVGA and VGA Extended Registers Instruction and Interrupt Control Registers 01000h −02FFFh Instpm OV0ADD Ssladd Display and Cursor Control Registers 70000h-7FFFFh VGA and Extended VGA Register Map Address Register Name Read Register Name Write 2D Registers VGA and Extended VGA I/O and Memory Register Map Indirect VGA and Extended VGA Register Indices Index Sym DescriptionIndex Sym Register Name 2D Attribute Controller Registers 3C0h / 3C1h CR0F Graphics Address Translation GTT Memory Buffers for GC’s Instruction Interface Graphics Translation Table GTT Range Definition This page is intentionally left blank Vendor Id Device Id PCI Device Characteristics Basic Initialization ProceduresInitialization Sequence Hardware Detection Probe Frame Buffer Initialization Hardware State Hardware Register InitializationColor vs. Monochrome Monitors Protect Registers Locking and Unlocking Saving the Hardware State Restoring the Hardware State Intel 815 Chipset Graphics Controller PRM, Rev Intel 815 Chipset Graphics Controller PRM, Rev This page is intentionally left blank When the Source and Destination Locations Overlap Blt Engine ProgrammingBLT Engine Programming Considerations Source Bblt3.vsd Destination Source Bblt4.vsd Contiguous vs. Discontinuous Graphics Data Basic Graphics Data Considerations Source Data Monochrome Source Data Pattern Data -- Always an 8x8 Array of Pixels Pattern Data Bpp Pattern Data -- Occupies 64 Bytes 8 quadwords Destination Data Pattern Fill -- a Very Simple BLT BLT Programming Examples Pattern Data for Example Pattern Fill BLT Results of Example Pattern Fill BLT On-Screen Destination for Example Character Drawing BLT Drawing Characters Using a Font Stored in System Memory Intel 815 Chipset Graphics Controller PRM, Rev Results of Example Character Drawing BLT Standard VGA Registers Initialization RegistersSmram Registers SMRAM-System Management RAM Control Register Device RAM Bit Description Initialization and Usage of Stolen Memory Clock Control and Power Management Registers LCD/TV-OutDisplay and Cursor Control Registers CRT Controller Registers 3B4h/3D4h/3B5h/3D5h Graphics Controller Registers 3CEh / 3CFh MSR Initialization Values for VGA Registers GR01 00h This page is intentionally left blank Frame Buffer Access Intel 815 Chipset Graphics Controller PRM, Rev General Control & Status Registers VGA and Extended VGA RegistersName Function Read Write Memory Offset Bit 1. ST00Input Status ST01Input Status Display Enable OutputBit Descriptions Vertical Retrace/Video Reserved. Read as Vsync Control FCRFeature Control MSRMiscellaneous Output CRT VSync PolarityCRT HSync Polarity SRXSequencer Index Sequencer Registers 2. SR00Sequencer Reset Shift 3. SR01Clocking Mode 4. SR02Plane/Map Mask 5. SR03Character Font Bit 32 Map Number Table LocationBit 10,4 Map Number Table Location Made according to the value of the Plane Mask Register SR02 6. SR04Memory Mode Register Graphics Controller Registers 7. SR07Horizontal Character Counter ResetGRXGRX Graphics Controller Index Register Bit Description Horizontal Character Counter 3. GR01Enable Set/Reset Register 2. GR00Set/Reset Register 5. GR03Data Rotate Register 4. GR02Color Compare Register 6. GR04Read Plane Select Register 7. GR05Graphics Mode Register Bits 65=00 Bits 65=01Bits 65=1x Odd/Even Mode Read ModeWrite Mode Graphics/Text Mode 8. GR06Miscellaneous RegisterBit 9. GR07Color Don’t Care Register 10. GR08Bit Mask RegisterBit Mask Packed Mode Enable Reserved To Local Memory Enable11. GR10Address Mapping VGA Buffer/Memory Map Select Supported 12. GR11Page Selector 13. GR141FSoftware Flags Memory Offset Address 3CFh Index=14h-1fh Default Attribute ARXAttribute Controller Index Register Attribute Controller Registers 3. AR10Mode Control Register 2. AR000FPalette Registers 0FPalette Bits P5, P4 Select Pixel Width/Clock Select Enable Line Graphics Character Code Enable Blinking/Select Background IntensityGraphics/Alphanumeric Mode Pixel Panning Compatibility 5. AR12Memory Plane Enable Register 4. AR11Overscan Color RegisterBit 54 ST01 Bit Reserved 6. AR13Horizontal Pixel Panning RegisterPixel Text Color Pixel Text Graphics 7. AR14Color Select Register VGA Color Palette Registers DACMASKPixel Data Mask Register DACRXPalette Read Index Register DACSTATEDAC State RegisterDACWXPalette Write Index Register Bits Index Register Indicated DACDATAPalette Data Register CRT Controller Register CRXCRT Controller Index Register Display Fields and Dimensions CRxx Control Registers 3. CR01Horizontal Display Enable End Register 2. CR00Horizontal Total Register4. CR02Horizontal Blanking Start Register Bit Amount of Delay 5. CR03Horizontal Blanking End Register6. CR04Horizontal Sync Start Register 7. CR05Horizontal Sync End Register 9. CR07Overflow Register 8. CR06Vertical Total Register 115 116 10. CR08Preset Row Scan Register 11. CR09Maximum Scan Line Register Double Scanning Enable 13. CR0BText Cursor End Register 12. CR0AText Cursor Start Register 14. CR0CStart Address High Register 16. CR0EText Cursor Location High Register 15. CR0DStart Address Low Register 18. CR10Vertical Sync Start Register 17. CR0FText Cursor Location Low Register 19. CR11Vertical Sync End Register CR13Offset Register 20. CR12Vertical Display Enable End Register 22. CR14Underline Location Register CR146 CR176 Addressing ModeCount By CR145 CR173 Address Incrementing Interval 24. CR16Vertical Blanking End Register 23. CR15Vertical Blanking Start Register 25. CR17CRT Mode Control Word Mode or Byte ModeCR146 CR176 Select Row Scan Counter Compatibility Mode Support Memory Address Counter Address Bits DWord Mode CR17 bit 1=1 CR17 bit 1=0 CR17 bit 0=1 CR17 bit 0=0 Frame Buffer Address Decoder 27. CR22Memory Read Latch Data Register 26. CR18Line Compare Register 29. CR30Extended Vertical Total Register 30. CR31Extended Vertical Display End Register 31. CR32Extended Vertical Sync Start Register 32. CR33Extended Vertical Blanking Start Register 33. CR35 Extended Horizontal Total Time Register 34. CR39Extended Horizontal Blank Time RegisterExtended Horizontal Total MSB that extends CR00 35. CR40Extended Start Address Register 37. CR42Extended Start Address High Register 36. CR41Extended Offset Register Interlace Enable 38. CR70Interlace Control Register39. CR80I/O Control 41. CR82Blink Rate Control 40. CR81Reserved Programming Interface Reserved Bits and Software CompatibilityOverview GC Instruction Streams GC Register ProgrammingInstruction Use Instruction Transport Overview Interrupt Ring Instruction Parser Ring Buffer Registers Ring Buffers RB Characteristic Description Ring Buffer InitializationRing Buffer Use Batch Buffer Sequence Batch Buffers Instruction Arbitration Arbitration RationaleWait Instructions Batch Buffer Protected Mode Instruction Arbitration PointsInstruction Arbitration Rules Instruction Format Instruction Parser InstructionsInstructions 3129 2824 210 Bits Client Instruction Graphics Controller Instructions Client Introduction Instruction Parser InstructionsInstruction Descriptions DWord Bit Description Opcode 01h Opcode 02hReserved MBZ DWord Bit Gfxcmdparserwaitforevent DWord Bits Description Opcode 15h Reserved 00000hDwordlength 00h Instruction Target 14h Flip type 0 Synch flip, 1 Async flipDword Length 00h Opcode 07h Opcode 16h Arbitration ON/OFF Opcode 08hInstruction Target 11h Instruction Target 12h Word Bits Description Instruction Target 30h Gfxcmdparserbatchbuffer Instructions BLTs To and From Cacheable MemoryBLT Engine Instructions Setupblt Setup Foreground Color SLB & TB only Setup Background Color AllInstruction Target Opcode 00h Dword Length 06h Dword Length 07h Instruction Target Opcode 10hColor Depth Raster Operation Instruction Target Opcode 20h PixelbltInstruction Target Opcode 21h Destination X2 Coordinate Ending Right Textblt Instruction Target Opcode 22hDword Length 04h Instruction Target Opcode 30h TEXTImmediateBLTImmediate Data DW Immediate Data DWs 2 through Dwordlength DWL Instruction Target Opcode 40h ColorbltDword Length 03h Solid Pattern Color Instruction Target Opcode 41h Patblt Monopatblt Mono Pattern Transparency Mode 1 = transparency enabledInstruction Target Opcode 42h Pattern Background Color Instruction Target Opcode 43h Srccopyblt Line Instruction Target Opcode 44h Source Foreground Color Source Background Color Instruction Target Opcode 61h Mono Source Transparency Mode 1 = transparency enabled Destination Transparency Mode See BR00 definition FullbltInstruction Target Opcode 45h Destination Transparency Color Fullmonosrcblt Instruction Target Opcode 46h Dword Length 09h Instruction Target Opcode 47h 181 Dword Length 0Ah Instruction Target Opcode 48h 183 12.3.1. BR00-BLT Opcode and Control BLT Engine Instruction Definitions 185 SolPat Rsvd Mono 187 12.3.4. BR03-Clip Rectangle Y2 Address 12.3.3. BR02-Clip Rectangle Y1 Address 3128 Reserved. Must be Zero 2716 12.3.5. BR04-Clip Rectangle X1 12.3.7. BR06-Setup Expansion Foreground Color 12.3.6. BR05-Setup Expansion Background Color 12.3.8. BR07-Setup Color Pattern Address 12.3.9. BR08-Destination X1 12.3.11. BR10-Destination Y2 Address 12.3.10. BR09-Destination Address and Destination Y1 Address Source Pitch Offset or Monochrome Source Quadwords 12.3.13. BR12-Source Address Increment/Decrement Select 12.3.14. BR13-BLT Raster OP, Control, and Destination Pitch Dynamic Color Depth Source Select Mode 12.3.15. BR14-Destination Width & Height 12.3.16. BR15-Color Pattern Address 3124 Reserved. Must be Zero 230 12.3.18. BR17-Pattern Expansion Foreground Color 12.3.20. BR19-Source Expansion Foreground Color DSLH-Destination Scan Line Height SSLADD-Source Scan Line Address DSLRADD-Destination Scan Line Read Address 204 Gfxprimitive Rendering Engine InstructionsAxis Aligned Rectangles Primitive Winding Order Position Mask BiasPrimitive Rendering Instruction Format Vertex Attribute Comments Variable Length Vertex Formats for Rendering Instructions Gfxvertex Gfxrenderstatevertexformat Rendering Block 1Eh GfxblockBlock Type Block Pattern Format DWord Bits Vertical Motion Vector Precision 00 = 1/2 pixelPrediction Type 212 Non-pipelined State Variables Motion Vector FormatPrecision Format Range Gfxrenderstatemaptexels Gfxrenderstatemapcoordsets Normalized Coordinate Set Mask 0 = Do not update 1 = Update Update Coordinate Set Index The valid range isOpcode 1h Normalized Coordinate Set Gfxrenderstatemapinfo Walk Discrete Integrated Base Utilize Fence Tiled Surface Dwordlength 2h 3DstateMW 1DhReserved 0h Surface Format 1511 Color Space Conversion Enable 221 Gfxrenderstatemapfilter Opcode 2h Reserved 00h Mip Mode Filter Valid values are Opcode 3h Gfxrenderstatemaplodlimits Texture LOD Dither Weight Mask 0 = Do not update 1 = Update GfxrenderstatemaplodcontrolOpcode 4h Gfxrenderstatemappaletteload 3DStateMWNPNon-pipelined 1DhOpcode 82h Blend Equation Description Gfxrenderstatemapcolorblendstages 3DState24 00h Update Blending Stage Index The valid range isWrite result to Current Register or Accumulator Select Replicate Arg1 Alpha to Color Channels Invert Color Arg2 Gfxrenderstatemapalphablendstages 3DState24 01h Invert Alpha Arg1Invert Alpha Arg2 Instruction 1h Gfxrenderstatecolorfactor Gfxrenderstatecolorchromakey Kill Pixel Mode KeyedPixelControl Write Mask 0 = Do not update 1 = Update Instruction 2hKeyedPixelControl Gfxrenderstatesrcdstblendmono No SpecularMonochrome Specular Full Color RGB 236 Opcode Source / Destination Blend State Alpha Reference State Mask 1 = Update 0 = Do Not Update Gfxrenderstatezbiasalphafuncref3DState24NP Non-pipelined 14h Gfxrenderstatelinewidthcullshade Mode Specular Shade Mode State Mask 1 = Update 0 = Do Not Update Alpha Shade Mode State Mask 1 = Update 0 = Do Not UpdateColor Shade Mode State Mask 1 = Update 0 = Do Not Update 2824 3DState24 02h Color Index Key Enable Mask 1 = Update 0 = Do Not Update Alpha Setup Enable Enable Mask 1 = Update 0 = Do Not UpdateSpecular Enable State Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA1 Frame Buffer Write Enable Mask 1 = Update 0 = Do Not Update Specular Dither Enable Mask 1 = Update 0 = Do Not UpdateBuffer Write Enable Mask 1 = Update 0 = Do Not Update GFXRENDERSTATEBOOLEANENA2 Gfxrenderstatefogcolor Gfxrenderstatedrawingrectangleinfo3DState24NP Non-pipelined 15h Opcode 80h 3DStateMWNP Non-pipelined 1Dh Scissor Rectangle Enable Mask 1 = Update 0 = Do Not Update Gfxrenderstatescissorenable3DState16NP Non-pipelined 1Ch Opcode 10h Opcode 81h Gfxrenderstatescissorrectangleinfo Stipple Pattern Opcode 83hStipple Pattern Gfxrenderstateantialiasing Vertex Sequence Gfxrenderstateprovokingvtxpixelization Rule Pixelization Rule Mask Small Triangle Filter Enable Mask Opcode 85h Gfxrenderstatedestbuffervariables Dest Buffer Format 0h = Any 8-bit Surface Drawing and Scissor Rectangles Programming Hints/Rules Color Calculator 255 256 Programming Notes Clock Control Registers Example Programming Sequence DCLK2 DCLK0D-Display Clock 0 Divisor Register DCLK1D-Display Clock 1 Divisor Register DCLK2D-Display Clock 2 Divisor Register LCDCLKD-LCD Clock Divisor Register DCLK0DS-Display & LCD Clock Divisor Select Register Post Divisor Select LCD ClockReserved VCO Loop Divide LCD Clock VCO Loop Divide clock Post Divisor Select clock Internal DAC Enable PWRCLKC-Power Management and Miscellaneous Clock Control Overlay Registers Comment Register/Instruction Category Updating Register Values 15.1. OV0ADD-Overlay 0 Register Update Address Register DOV0STA-Display/Overlay 0 Status Register GAMC50-Gamma Correction Registers Gamma Correction Green Blue Red Three times Mathematical Gamma Correction For Overlay Latch Address Gamma Correction Theory Of Operation Gamma Hardware Implementation Overlay Buffer Pointer Registers Memory Offset RegistersOBUF0Y-Overlay Buffer 0 Y Pointer Register Format Alignment OBUF0U-Overlay Buffer 0 U Pointer Register OBUF1Y-Overlay Buffer 1 Y Pointer Register OBUF0V-Overlay Buffer 0 V Pointer Register OBUF1U-Overlay Buffer 1 U Pointer RegisterBit Descriptiont Overlay Stride Registers OBUF1V-Overlay Buffer 1 V Pointer Register15.4.2.1. OV0STRIDE-Overlay 0 Stride Register YRGBVPH-Y/RGB Vertical Phase Register Overlay Initial Phase Registers HORZPH-Horizontal Phase Register UVVPH-UV Vertical Phase Register INITPH-Initial Phase Register Overlay Destination Window Position/Size Registers DWINPOS-Destination Window Position RegisterDWINSZ-Destination Window Size Register SWID-Source Width Register Overlay Source Size Registers SWIDQW-Source Width In QWords Register SHEIGHT-Source Height Register YRGBSCALE-Y/RGB Scale Factor Register Overlay Scale Factor Registers UVSCALE-UV Scale Factor Register Overlay Color Correction Registers 15.4.7.1. OV0CLRC0-Overlay 0 Color Correction 0 Register15.4.7.2. OV0CLRC1-Overlay 0 Color Correction 1 Register DCLRKV-Destination Color Key Value Register Overlay Destination Color Key Registers Destination Constant Alpha Blend Enable Always Constant Alpha Blend EnableDCLRKM-Destination Color Key Mask Register SCLRKVH-Source Color Key Value High Register Overlay Source Color Key Registers SCLRKM-Source Color Key Mask Register SCLRKVL-Source Color Key Value Low Register Source Constant Alpha Blend Enable 15.4.10.1. OV0CONF-Overlay Configuration Register Overlay Configuration Registers 15.4.11. OV0CMD-Overlay Command Register Vertical Luminance Filter. Vertical Luminance Filter Vertical Chrominance Filter. Vertical Chrominance Filter Manual flip command Source FormatAutomatic flipping 297 AWINPOS-Alpha Blend Window Position Register Overlay Alpha Blend Window Position/Size Registers AWINSZ-Alpha Blend Window Size Register Overlay Flip Instruction 300 Instruction, Memory, and Interrupt Control Registers Instruction Control RegistersFENCE-Graphics Memory Fence Table Registers Tile walk Reserved for address bits 31 downtoFence size Fence Pitch Normal Invalidation Mechanism PGTBLCTL-Page Table Control Register PGTBLER-Page Table Error Register Error Type PGTBLERRMSK-Page Table Error Mask Register Command Streamer DMA Page Table Error Mask Buffer Unit Page Table Error MaskOverlay Page Table Error Mask Display Page Table Error Mask Intel 810 Chipset and Intel815 Chipset Errata RINGBUF-Ring Buffer Registers Ring Buffer Valid Reserved DWord Description Offset HWSPGA-Hardware Status Page Address Register IPEHR-Instruction Parser Error Header Register debug IPEIR-Instruction Parser Error Identification Register debug INSTDONE-Instruction Stream Interface Done Register This read only register reports engine done signals NOPID-NOP Identification Register Disable State Variable Updates INSTPM-Instruction Parser Mode Register INSTPS-Instruction Parser State Register debug Cscpr State Machine Command Parser ABBSTR-Active Batch Buffer Start Address Register debug BBPPTR-Batch Buffer Parser Pointer Register debug ABBEND-Active Batch Buffer End Address Register debug DMAFADD-DMA Engine Fetch Address debugCurrent DMA Address Reserved User of the DMA Engine Reserved Host Graphics Prefetch Mode MEMMODE-Memory Interface Mode Register debugGraphics Address Translation Mode Instruction Fifo Debug Mode Bit Definition For Interrupt Control Registers Interrupt Control Registers 321 HWSTAM-Hardware Status Mask Register Interrupt Enables. See Table IER-Interrupt Enable Register Interrupt Identity. See. Table IIR-Interrupt Identity Register Interrupt Mask Bits. See. Table IMR-Interrupt Mask Register ISR-Interrupt Status Register Table Error handling in Intel 815 Chipset Error Identity, Mask and Status Registers Table Error Resetting the Page Table Error EMR-Error Mask Register EIR-Error Identity Register ESR-Error Status Register FWBLC-FIFO Watermark and Burst Length Control Display Interface Control 332 HTOTAL-Horizontal Total Register LCD / TV-Out Register Description HBLANK-Horizontal Blank Register HSYNC-Horizontal Sync Register VTOTAL-Vertical Total Register VBLANK-Vertical Blank Register VSYNC-Vertical Sync Register LCD / TV-Out Enable LCDTVC-LCD/TV-Out Control RegisterSync Polarity Control FP / 740 Data Ordering FP Vesa VGA ModeFpvsync Control Fphsync Control Fphsync Output Control Border EnableActive Data Order Active Data Polarity BCLRPAT- Border Color Pattern Register OVRACT-Overlay Active Register DRT-DRAM Row Type Local Memory Interface Bit RAS#-to-CAS# delay t RCD Reserved Paging Mode Control PMCDRAMCL-DRAM Control Low Bit RAS# act. To precharge t RAS Refresh to RAS# act. t RC DRAMCH-DRAM Control High 346 19. I/O Control Registers HVSYNC-HSYNC/VSYNC Control RegisterHSYNC/VSYNC Control1916 GPIOAGeneral Purpose I/O Control Register a Gpio Registers Value .bit GPIOBGeneral Purpose I/O Control Register B 351 352 Display And Cursor Registers DISPSL-Display Scan Line CountLine Counter for Display Inclusive / Exclusive DISPSLC-Display Scan Line Count Range Compare Reserved Display path Graphics Gamma Enable. See note PIXCONF-Pixel Pipeline ConfigurationOverlay path Gamma Enable. See note Pixel Pipeline Control Bit DAC Enable Display Color ModeEnable Extended Status Read Mode CRT Overscan Color Transition from VGA modes to hires mode or opposite GUI ModeBLTCNTL-BLT Control SWF13-Software Flag Registers DPLYBASE-Display Base Address Register Vertical Sync Status Enable Reserved Flat Panel Hot Plug Detect EnableDisplay Line Compare Enable DPLYSTAS-Display Status Select Register Overlay Registers Upated Enable Vertical Blank EnableOverlay Registers Updated Status Vertical Sync Status Hardware Cursor CURCNTR-Cursor Control RegisterReserved Cursor Coordinate System Origin Select CURPOS-Cursor Position Register CURBASE-Cursor Base Address Register Appendix a Mode Parameters Parameters for Screen Resolution/Refresh Rate 320x20070Hz = Parameters for Screen Resolution/Refresh Rate 320x24070Hz = Parameters for Screen Resolution/Refresh Rate 352X48070Hz = Parameters for Screen Resolution/Refresh Rate 352X57670Hz = Parameters for Screen Resolution/Refresh Rate 400x30070Hz = Parameters for Screen Resolution/Refresh Rate 512X38470Hz = Parameters for Screen Resolution/Refresh Rate 640x35085Hz = Parameters for Screen Resolution/Refresh Rate 640x40070Hz = Parameters for Screen Resolution/Refresh Rate 640x40085Hz = Parameters for Screen Resolution/Refresh Rate 640x48060Hz = Parameters for Screen Resolution/Refresh Rate 640x48070Hz = Parameters for Screen Resolution/Refresh Rate 640x48072Hz = Parameters for Screen Resolution/Refresh Rate 640x48075Hz = Parameters for Screen Resolution/Refresh Rate 640x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x40085Hz = Parameters for Screen Resolution/Refresh Rate 720x48060Hz = Parameters for Screen Resolution/Refresh Rate 720x48075Hz = Parameters for Screen Resolution/Refresh Rate 720x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x57660Hz = Parameters for Screen Resolution/Refresh Rate 720x57675Hz = Parameters for Screen Resolution/Refresh Rate 720x57685Hz = Parameters for Screen Resolution/Refresh Rate 800x60056Hz = Parameters for Screen Resolution/Refresh Rate 800x60060Hz = Parameters for Screen Resolution/Refresh Rate 800x60070Hz = Parameters for Screen Resolution/Refresh Rate 800x60072Hz = Parameters for Screen Resolution/Refresh Rate 800x60075Hz = Parameters for Screen Resolution/Refresh Rate 800x60085Hz = Parameters for Screen Resolution/Refresh Rate 854X48060Hz = Parameters for Screen Resolution/Refresh Rate 854X48075Hz = Parameters for Screen Resolution/Refresh Rate 854X48085Hz = 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 Intel around the world