Intel 815 manual PGTBLERRMSK-Page Table Error Mask Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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16.1.4.PGTBL_ERRMSK—Page Table Error Mask Register

Address Offset:	02028h (identical functionality in Device 0 at F0–F3h)
Default Value:	0000 0000h
Access:	Read/Write
Size:	32 bits

This register is new to the Intel® 815 chipset (i.e., not in the Intel® 810 chipset)

The bits in this register mask out the corresponding page table error, preventing it from being reported in the Page Table Error Register. The Page Table Error Register can only show one page table error and associated error type at a time, and the error reported is one with the highest priority amongst all current page table errors. This Page Table Error Mask Register can be used to mask out higher priority errors, such that a lower priority error can be reported if currently asserted.

Page table errors are reported with the following priority (highest to lowest): OS, DS, host, render, blit, mapping engine, CS, and BF. If any page table error occurs, the highest priority error that is not masked with the associated bit in this Page Table Error Mask Register, will be reported in the Page Table Error Register, along with the associated error type. All lower priority page table errors will not be reported.

Procedure for determining if a particular type of low-priority page table error has occurred:

1.Bit 4 of the Error Status Register will be a 1 if any page table error has occurred.

2.Mask out all page table errors by writing 000000FFh to the Page Table Error Mask Register – this is done because the Error Status Register bit 4 will not be cleared if any page table error is asserted.

3.Unmask the target page table error by writing a 0 to the associated bit in the Page Table Error Mask Register.

4.Read bit 4 of the Error Status Register. If it is a 1, then the target page table error has occurred and the values reported in the Page Table Error Register are valid. Otherwise, the target page table error has not occurred.

31						9	8
			Reserved				BF Error
							Mask
7	6	5	4	3	2	1	0
CS DMA	OS Error	DS Error	Host Error	Render	TL Blit	NC Blit	ME Error
Error	Mask	Mask	Mask	Error	Error	Error	Mask
Mask				Mask	Mask	Mask

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