Intel 815 manual 6. GR04Read Plane Select Register, 7. GR05Graphics Mode Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.3.6.GR04Read Plane Select Register

I/O (and Memory Offset) Address:				3CFh (Index=04h)
Default:				0Uh (U=Undefined)
Attributes:				Read/Write
7				2	1	0
			Reserved (000000)			Read Plane Select
		Bit		Description
	7:2		Reserved. Read as 0s.
	1:0		Read Plane Select. These two bits select the memory plane from which the processor reads data in
			Read Mode 0. In Odd/Even Mode, bit 0 of this register is ignored. In Chain 4 Mode, both bits 1 and 0 of
			this register are ignored. The four memory planes are selected as follows:
			00 = Plane 0
			01 = Plane 1
			10 = Plane 2
			11 = Plane 3
			These two bits also select which of the four memory read latches may be read via the Memory read
			Latch Data Register (CR22). The choice of memory read latch corresponds to the choice of plane
			specified in the table above. The Memory Read Latch Data register and this additional function served
			by 2 bits are features of the VGA standard that were never documented by IBM.

9.3.7.GR05Graphics Mode Register

I/O (and Memory Offset) Address:				3CFh (Index=05h)
Default:				0UUU U0UUb (U=Undefined)
Attributes:				Read/Write
7		6	5	4	3	2	1	0
	Reserved		Shift Register Control	Odd/Even	Read	Reserved		Write Mode
	(0)				Mode	(0)
	Bit				Description

7Reserved. Read as 0s.

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