Intel 815 manual VGA and Extended VGA Registers, General Control & Status Registers, Offset

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.VGA and Extended VGA Registers

This chapter describes the registers and the functional operation notations for the observable registers in the 2D section. Each register is documented and the various bit settings defined. It is important to note that not all combinations of bit settings result in functional operating modes. Note that these registers can be accessed via either I/O space or memory space. The memory space addresses listed are offsets from the base memory address programmed into the MMAPA register (PCI configuration offset 14h). For each register, the memory mapped address offset is the same address value as the I/O address.

9.1.General Control & Status Registers

The setup, enable and general registers are all directly accessible by the processor. A sub indexing scheme is not used to read from and write to these registers.

Name	Function		Read			Write
		I/O		Memory	I/O		Memory Offset
				Offset
ST00	VGA Input Status Register 0	3C2h		3C2h			
ST01	VGA Input Status Register 1	3BAh/3DAh1		3BAh/3DAh1			
FCR	VGA Feature Control Register	3CAh		3CAh	3BAh/3DAh1		3BAh/3DAh1
MSR	VGA Miscellaneous Output	3CCh		3CCh	3C2h		3C2h
	Register
NOTES:

1.The address selection for ST01 reads and FCR writes is dependent on CGA or MDA emulation mode as selected via the MSR register.

Various bits in these registers provide control over and the real-time status of the horizontal sync signal, the horizontal retrace interval, the vertical sync signal, and the vertical retrace interval.

The horizontal retrace interval is the period during the drawing of each scan line containing active video data, when the active video data is not being displayed. This period includes the horizontal front and back porches, and the horizontal sync pulse. The horizontal retrace interval is always longer than the horizontal sync pulse.

The vertical retrace interval is the period during which the scan lines not containing active video data are drawn. It is the period that includes the vertical front and back porches, and the vertical sync pulse. The vertical retrace interval is always longer than the vertical sync pulse.

Display Enable is a status bit (bit 0) in VGA Input Status Register 1 that indicates when either a horizontal retrace interval or a vertical retrace interval is taking place. In the IBM* EGA graphics system (and the ones that preceded it, including MDA and CGA), it was important to check the status of this bit to ensure that one or the other retrace intervals was taking place before reading from or writing to the frame buffer. In these earlier systems, reading from or writing to frame buffer at times outside the retrace intervals meant that the CRT controller would be denied access to the frame buffer in while accessing pixel data needed to draw pixels on the display. This resulted in either “snow” or a flickering display. The term “Display Enable” is an inaccurate description for this status bit, since the name suggests a connection to the enabling or disabling the graphics system.

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