Intel 815 manual Discrete Integrated Base Utilize Fence Tiled Surface, Walk

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

Discrete	Integrated	Base	Utilize Fence	Fence	Tiled	Tile	Surface
Device	Device	Address Bits	Registers	Range Hit	Surface	Walk
		[31:26]
✔	✔	All Zeros	Yes	No	⊗	⊗	Linear
✔	✔	All Zeros	Yes	Yes	⊗	⊗	Tiled*
	✔	All Zeros	No	⊗	No	⊗	Linear
	✔	All Zeros	No	⊗	Yes	✔	Tiled
✔		Any Bit Set	⊗	⊗	No	⊗	Linear
✔		Any Bit Set	⊗	⊗	Yes	✔	Tiled

* The pitch specified in this instruction must be the same as the pitch in the corresponding fence register

Surfaces that contain mip-maps are located within a single rectangular area of memory identified by the base address of the upper left corner and a pitch. The pitch must be specified at least as large as the next power of two, equal to or greater than the widest mip-map. These surfaces may be overlapped in memory and must adhere to the following memory organization rules:

•The Base Address must be 4 KB aligned.

•Each successively smaller mip-map must lie vertically below and left aligned.

•Each mip-map must have its upper left corner vertically aligned to an even quadword address.

The following figures show an example of a 32x8 @ 16 bpt and a 4x8 @ 16 bpt map where the dashed lines identify quadwords.

Figure 34	Mip-map Surface Organization Example
	0
	1	Base Address
	2
	3	32x8
	4
			0
	5
	6		1
	7		2
	8		3	4x8
	9	16x4	4
	10		5
	11		6
	12	8x2	7
	13		8
				2x4
	14	4x1	9
	15	2x1	10
	16		11	1x2
	17		12
	18	1x1	13	1x1
	19		14
	20		15

218