Intel 815 manual 7. CR05Horizontal Sync End Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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9.6.7.CR05Horizontal Sync End Register

I/O (and Memory Offset) Address:			3B5h/3D5h (index=05h)
Default:			00h
Attributes:			Read/Write (Group 0 Protection)
7	6	5	4	0

Hor Blank	Horizontal Sync Delay
End Bit 5

Horizontal Sync End

Bit		Description
7	Horizontal Blanking End Bit 5. This bit provides the most significant bit of a 6-bit value that specifies
	the end of the horizontal blanking period relative to its beginning. Bits [4:0] of Horizontal Blanking End
	Register (CR03) supplies the 5 least significant bits. See CR03[4:0] for further details.
	This 6-bit value should be set to the least significant 6 bits of the result of adding the length of the
	blanking period in terms of character clocks to the value specified in the Horizontal Blanking Start
	Register (CR02).
6:5	Horizontal Sync Delay. This field defines the degree to which the start and end of the horizontal sync
	pulse are delayed to compensate for internal pipeline delays. This capability is supplied to implement
	VGA compatibility. These field describes the delay in terms of a number character clocks.
	Bit [6:5]	Amount of Delay
	00	no delay
	01	delayed by 1 character clock
	10	delayed by 2 character clocks
	11	delayed by 3 character clocks
4:0	Horizontal Sync End. This field provides the 5 least significant bits of a 5-bit value that specifies the
	end of the horizontal sync pulse relative to its beginning. A value equal to the 5 least significant bits of
	the horizontal character counter value at which time the horizontal retrace signal becomes inactive
	(logical 0). Thus, this 5-bit value specifies the width of the horizontal sync pulse.
	To obtain a retrace signal of W, the following algorithm is used:
	Value of Horizontal Sync start Register (CR04) + width of horizontal retrace signal in character clock
	units = 5 bit result to be programmed in this field

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