Intel 815 manual Saving the Hardware State

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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5.6.Saving the Hardware State

Note that the VGA register unlocking protocol must be performed in order to access some of the registers described below.

During a state change, the driver should preserve the following registers to provide complete state restoration in the future:

•	IO Control	CR80
•	Address Mapping	GR10
•	Bit Blit Control	MM 0x7000C
•	Video Clock 2 / M	MM 0x6008
•	Video Clock 2 / N	MM 0x600C
•	Video Clock 2 / Divisor Select	MM 0x6012
•	Vertical Total	CRX 30
•	Vertical Display End	CRX 31
•	Vertical Sync Start	CRX 32
•	Vertical Blank Start	CRX 33
•	Horizontal Total	CRX 35
•	Horizontal Blnk	CRX 39
•	Ext Offset	CRX 41
•	Interlace Control	CRX 70
•	Hardware Status Mask Register	MM 0x2098
•	Interrupt Enable Register	MM 0x20A0
•	Interrupt Identity Register	MM 0x20A4
•	Interrupt Mask Register	MM 0x20A8
•	Error Mask Register	MM 0x20B4
•	Display Control Register	MM 0x70008
•	Pixel Pipeline Configuration 0 Register	MM 0x70009
•	Pixel Pipeline Configuration 1 Register	MM 0x7000A
•	Pixel Pipeline Configuration 2 Register	MM 0x7000B
•	Watermark and Burstlength Control	MM 0x20D8
•	Low-priority ring information	MM 0x2030 – 0x203F

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