5. CR03Horizontal Blanking End Register

9.6.5.CR03Horizontal Blanking End Register

I/O (and Memory Offset) Address:				3B5h/3D5h (index=03h)
Default:				1UUU UUUUb (U=Undefined)
Attributes:				Read/Write (Group 0 Protection)
7		6	5	4	0
	Reserved		Display Enable Skew	Horizontal Blanking End Bits 4:0

(0)Control

Bit		Description

7	Reserved. Values written to this bit are ignored, and to maintain consistency with the VGA standard, a
	value of 1 is returned when this bit is read. At one time, this bit was used to enable access to certain
	light pen registers. At that time, setting this bit to 0 provided this access, but setting this bit to 1 was
	necessary for normal operation.

6:5	Display Enable Skew Control. Defines the degree to which the start and end of the active display area
	are delayed along the length of a scan line to compensate for internal pipeline delays. These 2 bits
	describe the delay in terms of a number character clocks.
	Bit [6:5]	Amount of Delay
	00	no delay
	01	delayed by 1 character clock
	10	delayed by 2 character clocks
	11	delayed by 3 character clocks

4:0	Horizontal Blanking End Bits [4:0]. This field provides the 5 least significant bits of a 6-bit value that
	specifies the end of the blanking period relative to its beginning on a single scan line. Bit 7 of the
	Horizontal Sync End Register (CR05) supplies the most significant bit.
	This 6-bit value should be programmed to be equal to the least significant 6 bits of the result of adding
	the length of the blanking period in terms of character clocks to the value specified in the Horizontal
	Blanking Start Register (CR02).

This register is used to specify the beginning of the horizontal sync pulse relative to the beginning of the active display area on a scan line.

Bit	Description

7:0	Horizontal Sync Start. This field should be set equal to the number of character clocks that occur from
	beginning of the active display area to the beginning of the horizontal sync pulse on a single scan line.

112