Intel 815 manual Ring Buffers RB, Ring Buffer Registers

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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10.4.4.Ring Buffers (RB)

The GC provides two Ring Buffer (RB) mechanisms through which instructions can be passed to the Instruction Parser. They are referred to as the Interrupt and Low-Priority RBs, and are basically identical, except for differences in arbitration rules and priority.

Figure 27. Ring Buffers

	Graphics Memory
		Wrap Around
		Starting Addres
Buffer	Low Priority Ring	Head Pointer
Length	Buffer	DMA Pointer
		Tail Pointer
		Starting Addres
Buffer	Interrupt Ring	Head Pointer
Length	Buffer	DMA Pointer
		Tail Pointer
		RingBuf.vsd

10.4.4.1.Ring Buffer Registers

A Ring Buffer is defined by a set of two Ring Buffer registers—Low and High Priority. Before an RB can be used for instruction transport, software needs to program these registers. The fields contained within these registers are as follows:

•Ring Buffer Valid: This bit controls whether the RB is included in the instruction arbitration process. Software must program all other RB parameters before enabling an RB. An RB can be disabled and later re-enabled. Enabling or disabling an RB does not, of itself, change any other RB register fields.

•Start Address: This field points to a contiguous, 4 KB-aligned, linear (e.g., not tiled) memory address region which provides the actual instruction buffer area.

•Buffer Length: The size of the buffer, in 4KB increments, up to 2MB.

•Head Offset: This is the DWord offset (from Start Address) of the next instruction that the IP will execute. The IP will update this field as instructions are retired. (Note that, if instructions are pending execution, the IP will likely have fetched instructions past the Head Offset). As the GC does not "reset" the Head Offset when an RB is enabled, software must program the Head Offset field before enabling the Ring Buffer. Although this allows software to enable an RB with any valid values for Head/Tail (i.e., can enable or re-enable the RB with instructions already pending), it is anticipated that software will initialize the Head Offset to 0. Once the Head Offset reaches the Tail Offset (Head = Tail), the IP considers the RB empty.

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