Intel 815 manual GC Register Programming, GC Instruction Streams, Instruction Use

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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10.3.GC Register Programming

All of the GC registers (except for the PCI Configuration registers) are memory mapped. The base address of this 512 KB memory block is programmed in the MMADR PCI Configuration register. Note that 2D control registers (VGA and Extended VGA registers) are also located at their standard I/O locations. For more information on the registers, refer to the System Address Map chapter.

10.4.GC Instruction Streams

This section describes how instruction streams can be used to control GC operation and perform GC operations.

10.4.1.Instruction Use

GC instructions are used to control drawing engines and various GC functional units:

•3D Instructions. 3D instructions are used to program the 3D pipeline state and perform 3D rendering operations, including "StretchBlt" operations.

•Motion Compensation. A special "GFXBLOCK" instruction is used to perform Motion Compensation operations via the Mapping Engine.

•2D Instructions (BLT). These instructions are used to perform BLT operations.

•Instruction Parser (IP) Instructions. The IP instructions can be used to control and synchronize the instruction stream as well as perform various GC auxiliary functions (e.g., define graphics buffer attributes, perform display/overlay flips, etc.)

10.4.2.Instruction Transport Overview

Instructions are not written directly to the GC; instead, they are placed in memory by software and later read (via DMA) by the GC's Instruction Parser unit. The primary mechanism used to transport instructions is through the use of two ring buffers (RB): Low Priority RB and Interrupt RB. A secondary mechanism for instruction transport is through the use of batch buffers. The IP uses a set of rules to determine the order in which instructions are executed. Following sections in this chapter provide descriptions of the ring buffers, batch buffers, and IP rules.

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