Intel 815 manual DCLK2D-Display Clock 2 Divisor Register

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

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14.4.DCLK_2D—Display Clock 2 Divisor Register

Address Offset:	06008h–0600Bh
Default Value:	00030013h
Attribute:	R/W
Size:	32 bits

The Display Clock 2 Divisor register and Display & LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer.

Data is written to Display Clock 2 Divisor register followed by a write to the Clock 2 byte of the Display & LCD Clock Divisor Select Register. The completion of the write to the Display & LCD Clock Divisor Select Register causes data from both registers to transfer to the VCO register file simul- taneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence.

31			26	25	16	15	10	9	0
	Reserved			VCO 2 N-Divisor		Reserved		VCO 2 M-Divisor
Bit						Description
31:26		Reserved.
25:16		VCO 2	N-Divisor.N-Divisor value calculated for the desired output frequency. (default = 03h)
15:10		Reserved.
9:0		VCO 2	M-Divisor.M-Divisor value calculated for the desired output frequency. (default = 13h)

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