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Intel 815 manual Pixel Pipeline Control, PIXCONF-Pixel Pipeline Configuration

Models: 815

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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

R

20.3.Pixel Pipeline Control

20.3.1.PIXCONF—Pixel Pipeline Configuration

Memory Offset Address:

70008h

Default:

00000000h

Attributes:

Read/Write

31

28

27

26

25

24

Reserved (0000)

Display

Overlay

Reserved

Reserved

Gamma

Gamma

Enable

Enable

23

21

20

19

16

Reserved (000)

CRT

Display Color Mode

Control

15

14

13

12

11

10

9

8

8-Bit DAC

Reserved

Cursor

Extended

CRT

Reserved

Palette

Enable

Display

Status

Overscan

Addr

Enable

Read

Color

7

5

4

3

2

1

0

Reserved (000)

Reserved

Reserved

Reserved

VGA Wrap

GUI Mode

(0)

(System

(0)

Write 32)

Bit

Descriptions

31:28

Reserved (0000).

27

Display path (Graphics) Gamma Enable. (See note.)

0 = 16 and 24 BPP graphics data bypasses palette (default).

1 = 16 and 24 BPP graphics data goes through palette.

26

Overlay path Gamma Enable. (See note.)

0 = Video data bypasses palette (default).

1 = Video data goes through the palette. Useful when Alpha Blending the Overlay with the Primary

Display to provide gamma correction for the display device. The Overlay Gamma Correction

should be set up to un-gamma the overlay surface bringing it into the linear space before

performing the alpha blending. Both the primary display (27 = 1) and the Overlay (26=1) should

be passed through the palette after alpha blending to provide proper gamma correction for the

display device.

25:21

Reserved (00000).

20

CRT Control Signal Delay. This bit affects CRT Display enable and CRT Blank signal delay with

respect to CRT HSYNC and CRT VSYNC when the standard VGA pixel pipeline is used by CRT

display engine. This bit has no effect on Flat Panel centering or optimized timing modes.

0 = CRT Display Enable and CRT Blank are delayed for standard VGA compatibility (default).

1 = CRT Display Enable and CRT Blank are not delayed.

355

Image 355

Intel 815 manual Pixel Pipeline Control, PIXCONF-Pixel Pipeline Configuration, Overlay path Gamma Enable. See note

Contents

Programmer’s Reference Manual PRM Intel 815 Chipset Graphics ControllerIntel 815 Chipset Graphics Controller PRM, Rev Contents 100 106 141 Monosrccopyimmediateblt Gfxrenderstatemaplodlimits 15.4.3.3 HORZPH-Horizontal Phase Register 279 15.4.3.4 16.2.5 Figures Tables Rev Revision HistoryDate This page is intentionally left blank Terminology IntroductionTerm Description MCH Reference DocumentsIntel 815 Chipset Overview Intel 82815 Chipset Gmch Overview I/O Controller HubHost Interface Intel 82815 Chipset Gmch Block DiagramSystem Memory Interface Data Rate Signaling LevelMultiplexed AGP and Display Cache Interface Intel 82815 Chipset Gmch Integrated Graphics Support Hub InterfaceFront Side Bus System Memory Display Cache Interface Gmch Power DeliveryThree PCI Devices on Gmch System ClockingMulti-Mode Capability Requirements Supported Single Monitor and Multi-monitor ConfigurationsConfiguration Single Monitor Multi-monitor System Startup Device Mode Auto-Detect FlowchartSoftware Start-Up Sequence Graphics Driver Startup Switching Device modes System Memory Space System Address MapGraphics Controller Register Memory and I/O Map Memory and I/O Space RegistersReserved 50000h−5FFFFh. Reserved in the Intel 815 chipset Instruction and Interrupt Control Registers 01000h −02FFFh Address Offset Symbol Register Name AccessGC Register Memory Address Map VGA and VGA Extended RegistersInstpm OV0ADD Ssladd Display and Cursor Control Registers 70000h-7FFFFh VGA and Extended VGA Register MapAddress Register Name Read Register Name Write 2D Registers VGA and Extended VGA I/O and Memory Register MapIndex Sym Description Indirect VGA and Extended VGA Register IndicesIndex Sym Register Name 2D Attribute Controller Registers 3C0h / 3C1h CR0F Graphics Address Translation GTT Memory Buffers for GC’s Instruction InterfaceGraphics Translation Table GTT Range Definition This page is intentionally left blank Hardware Detection Probe Basic Initialization ProceduresVendor Id Device Id PCI Device Characteristics Initialization SequenceFrame Buffer Initialization Protect Registers Locking and Unlocking Hardware Register InitializationHardware State Color vs. Monochrome MonitorsSaving the Hardware State Restoring the Hardware State Intel 815 Chipset Graphics Controller PRM, Rev Intel 815 Chipset Graphics Controller PRM, Rev This page is intentionally left blank Blt Engine Programming When the Source and Destination Locations OverlapBLT Engine Programming Considerations Source Bblt3.vsd Destination Source Bblt4.vsd Contiguous vs. Discontinuous Graphics Data Basic Graphics Data ConsiderationsSource Data Monochrome Source Data Pattern Data -- Always an 8x8 Array of Pixels Pattern DataBpp Pattern Data -- Occupies 64 Bytes 8 quadwords Destination Data Pattern Fill -- a Very Simple BLT BLT Programming ExamplesPattern Data for Example Pattern Fill BLT Results of Example Pattern Fill BLT On-Screen Destination for Example Character Drawing BLT Drawing Characters Using a Font Stored in System MemoryIntel 815 Chipset Graphics Controller PRM, Rev Results of Example Character Drawing BLT SMRAM-System Management RAM Control Register Device Initialization RegistersStandard VGA Registers Smram RegistersRAM Bit DescriptionInitialization and Usage of Stolen Memory LCD/TV-Out Clock Control and Power Management RegistersDisplay and Cursor Control Registers CRT Controller Registers 3B4h/3D4h/3B5h/3D5h Graphics Controller Registers 3CEh / 3CFhMSR Initialization Values for VGA RegistersGR01 00h This page is intentionally left blank Frame Buffer Access Intel 815 Chipset Graphics Controller PRM, Rev Offset VGA and Extended VGA RegistersGeneral Control & Status Registers Name Function Read Write MemoryBit 1. ST00Input StatusVertical Retrace/Video Display Enable OutputST01Input Status Bit DescriptionsReserved. Read as Vsync Control FCRFeature ControlCRT VSync Polarity MSRMiscellaneous OutputCRT HSync Polarity SRXSequencer Index Sequencer Registers2. SR00Sequencer Reset Shift 3. SR01Clocking Mode4. SR02Plane/Map Mask Bit 32 Map Number Table Location 5. SR03Character FontBit 10,4 Map Number Table Location Made according to the value of the Plane Mask Register SR02 6. SR04Memory Mode RegisterBit Description Horizontal Character Counter 7. SR07Horizontal Character Counter ResetGraphics Controller Registers GRXGRX Graphics Controller Index Register3. GR01Enable Set/Reset Register 2. GR00Set/Reset Register5. GR03Data Rotate Register 4. GR02Color Compare Register6. GR04Read Plane Select Register 7. GR05Graphics Mode RegisterBits 65=01 Bits 65=00Bits 65=1x Read Mode Odd/Even ModeWrite Mode 8. GR06Miscellaneous Register Graphics/Text ModeBit 10. GR08Bit Mask Register 9. GR07Color Don’t Care RegisterBit Mask VGA Buffer/Memory Map Select Reserved To Local Memory EnablePacked Mode Enable 11. GR10Address MappingSupported 12. GR11Page Selector13. GR141FSoftware Flags Memory Offset Address 3CFh Index=14h-1fh Default AttributeARXAttribute Controller Index Register Attribute Controller RegistersPixel Width/Clock Select 2. AR000FPalette Registers 0F3. AR10Mode Control Register Palette Bits P5, P4 SelectPixel Panning Compatibility Enable Blinking/Select Background IntensityEnable Line Graphics Character Code Graphics/Alphanumeric Mode4. AR11Overscan Color Register 5. AR12Memory Plane Enable RegisterBit 54 ST01 Bit Pixel Text Graphics 6. AR13Horizontal Pixel Panning RegisterReserved Pixel Text Color7. AR14Color Select Register VGA Color Palette RegistersDACMASKPixel Data Mask Register Bits Index Register Indicated DACSTATEDAC State RegisterDACRXPalette Read Index Register DACWXPalette Write Index RegisterDACDATAPalette Data Register CRT Controller RegisterCRXCRT Controller Index Register Display Fields and Dimensions CRxx Control Registers2. CR00Horizontal Total Register 3. CR01Horizontal Display Enable End Register4. CR02Horizontal Blanking Start Register 5. CR03Horizontal Blanking End Register Bit Amount of Delay6. CR04Horizontal Sync Start Register 7. CR05Horizontal Sync End Register 9. CR07Overflow Register 8. CR06Vertical Total Register115 116 10. CR08Preset Row Scan Register 11. CR09Maximum Scan Line Register Double Scanning Enable13. CR0BText Cursor End Register 12. CR0AText Cursor Start Register14. CR0CStart Address High Register 16. CR0EText Cursor Location High Register 15. CR0DStart Address Low Register18. CR10Vertical Sync Start Register 17. CR0FText Cursor Location Low Register19. CR11Vertical Sync End Register CR13Offset Register 20. CR12Vertical Display Enable End RegisterCR145 CR173 Address Incrementing Interval CR146 CR176 Addressing Mode22. CR14Underline Location Register Count By24. CR16Vertical Blanking End Register 23. CR15Vertical Blanking Start RegisterWord Mode or Byte Mode 25. CR17CRT Mode ControlCR146 CR176 Select Row Scan Counter Compatibility Mode SupportMemory Address Counter Address Bits DWord ModeCR17 bit 1=1 CR17 bit 1=0 CR17 bit 0=1 CR17 bit 0=0 Frame Buffer Address Decoder27. CR22Memory Read Latch Data Register 26. CR18Line Compare Register29. CR30Extended Vertical Total Register 30. CR31Extended Vertical Display End Register 31. CR32Extended Vertical Sync Start Register 32. CR33Extended Vertical Blanking Start Register 34. CR39Extended Horizontal Blank Time Register 33. CR35 Extended Horizontal Total Time RegisterExtended Horizontal Total MSB that extends CR00 35. CR40Extended Start Address Register 37. CR42Extended Start Address High Register 36. CR41Extended Offset Register38. CR70Interlace Control Register Interlace Enable39. CR80I/O Control 41. CR82Blink Rate Control 40. CR81ReservedReserved Bits and Software Compatibility Programming InterfaceOverview Instruction Transport Overview GC Register ProgrammingGC Instruction Streams Instruction UseInterrupt Ring Instruction ParserRing Buffer Registers Ring Buffers RBRing Buffer Initialization Characteristic DescriptionRing Buffer Use Batch Buffer Sequence Batch BuffersArbitration Rationale Instruction ArbitrationWait Instructions Instruction Arbitration Points Batch Buffer Protected ModeInstruction Arbitration Rules Instruction Parser Instructions Instruction FormatInstructions 3129 2824 210 BitsClient Instruction Graphics Controller InstructionsClient DWord Bit Description Instruction Parser InstructionsIntroduction Instruction DescriptionsOpcode 02h Opcode 01hReserved MBZ DWord Bit GfxcmdparserwaitforeventDWord Bits Description Reserved 00000h Opcode 15hDwordlength 00h Flip type 0 Synch flip, 1 Async flip Instruction Target 14hDword Length 00h Opcode 07h Opcode 16hInstruction Target 12h Opcode 08hArbitration ON/OFF Instruction Target 11hWord Bits Description Instruction Target 30h GfxcmdparserbatchbufferBLTs To and From Cacheable Memory InstructionsBLT Engine Instructions Setupblt Dword Length 06h Setup Background Color AllSetup Foreground Color SLB & TB only Instruction Target Opcode 00hRaster Operation Instruction Target Opcode 10hDword Length 07h Color DepthDestination X2 Coordinate Ending Right PixelbltInstruction Target Opcode 20h Instruction Target Opcode 21hInstruction Target Opcode 22h TextbltDword Length 04h Immediate Data DWs 2 through Dwordlength DWL TEXTImmediateBLTInstruction Target Opcode 30h Immediate Data DWSolid Pattern Color ColorbltInstruction Target Opcode 40h Dword Length 03hInstruction Target Opcode 41h PatbltPattern Background Color Mono Pattern Transparency Mode 1 = transparency enabledMonopatblt Instruction Target Opcode 42hInstruction Target Opcode 43h SrccopybltLine Instruction Target Opcode 44hSource Foreground Color Source Background ColorInstruction Target Opcode 61h Mono Source Transparency Mode 1 = transparency enabledFullblt Destination Transparency Mode See BR00 definitionInstruction Target Opcode 45h Destination Transparency Color FullmonosrcbltInstruction Target Opcode 46h Dword Length 09h Instruction Target Opcode 47h181 Dword Length 0Ah Instruction Target Opcode 48h183 12.3.1. BR00-BLT Opcode and Control BLT Engine Instruction Definitions185 SolPat Rsvd Mono 187 12.3.4. BR03-Clip Rectangle Y2 Address 12.3.3. BR02-Clip Rectangle Y1 Address3128 Reserved. Must be Zero 2716 12.3.5. BR04-Clip Rectangle X112.3.7. BR06-Setup Expansion Foreground Color 12.3.6. BR05-Setup Expansion Background Color12.3.8. BR07-Setup Color Pattern Address 12.3.9. BR08-Destination X1 12.3.11. BR10-Destination Y2 Address 12.3.10. BR09-Destination Address and Destination Y1 AddressSource Pitch Offset or Monochrome Source Quadwords 12.3.13. BR12-Source Address Increment/Decrement Select 12.3.14. BR13-BLT Raster OP, Control, and Destination PitchDynamic Color Depth Source Select Mode12.3.15. BR14-Destination Width & Height 12.3.16. BR15-Color Pattern Address 3124 Reserved. Must be Zero 230 12.3.18. BR17-Pattern Expansion Foreground Color12.3.20. BR19-Source Expansion Foreground Color DSLH-Destination Scan Line Height SSLADD-Source Scan Line AddressDSLRADD-Destination Scan Line Read Address 204 Primitive Winding Order Rendering Engine InstructionsGfxprimitive Axis Aligned RectanglesBias Position MaskPrimitive Rendering Instruction Format Vertex Attribute Comments Variable Length Vertex Formats for Rendering InstructionsGfxvertex Gfxrenderstatevertexformat Block Pattern Format GfxblockRendering Block 1Eh Block TypeVertical Motion Vector Precision 00 = 1/2 pixel DWord BitsPrediction Type 212 Motion Vector Format Non-pipelined State VariablesPrecision Format Range Gfxrenderstatemaptexels Gfxrenderstatemapcoordsets Normalized Coordinate Set Update Coordinate Set Index The valid range isNormalized Coordinate Set Mask 0 = Do not update 1 = Update Opcode 1hGfxrenderstatemapinfo Walk Discrete Integrated Base Utilize Fence Tiled SurfaceSurface Format 3DstateMW 1DhDwordlength 2h Reserved 0h1511 Color Space Conversion Enable221 Gfxrenderstatemapfilter Opcode 2h Reserved 00h Mip Mode Filter Valid values areOpcode 3h GfxrenderstatemaplodlimitsGfxrenderstatemaplodcontrol Texture LOD Dither Weight Mask 0 = Do not update 1 = UpdateOpcode 4h 3DStateMWNPNon-pipelined 1Dh GfxrenderstatemappaletteloadOpcode 82h Blend Equation Description GfxrenderstatemapcolorblendstagesReplicate Arg1 Alpha to Color Channels Update Blending Stage Index The valid range is3DState24 00h Write result to Current Register or Accumulator SelectInvert Color Arg2 Gfxrenderstatemapalphablendstages Invert Alpha Arg1 3DState24 01hInvert Alpha Arg2 Instruction 1h GfxrenderstatecolorfactorGfxrenderstatecolorchromakey Kill Pixel ModeInstruction 2h KeyedPixelControl Write Mask 0 = Do not update 1 = UpdateKeyedPixelControl No Specular GfxrenderstatesrcdstblendmonoMonochrome Specular Full Color RGB 236 Opcode Source / Destination Blend State Gfxrenderstatezbiasalphafuncref Alpha Reference State Mask 1 = Update 0 = Do Not Update3DState24NP Non-pipelined 14h Gfxrenderstatelinewidthcullshade Mode 2824 3DState24 02h Alpha Shade Mode State Mask 1 = Update 0 = Do Not UpdateSpecular Shade Mode State Mask 1 = Update 0 = Do Not Update Color Shade Mode State Mask 1 = Update 0 = Do Not UpdateGFXRENDERSTATEBOOLEANENA1 Alpha Setup Enable Enable Mask 1 = Update 0 = Do Not UpdateColor Index Key Enable Mask 1 = Update 0 = Do Not Update Specular Enable State Mask 1 = Update 0 = Do Not UpdateGFXRENDERSTATEBOOLEANENA2 Specular Dither Enable Mask 1 = Update 0 = Do Not UpdateFrame Buffer Write Enable Mask 1 = Update 0 = Do Not Update Buffer Write Enable Mask 1 = Update 0 = Do Not UpdateGfxrenderstatedrawingrectangleinfo Gfxrenderstatefogcolor3DState24NP Non-pipelined 15h Opcode 80h 3DStateMWNP Non-pipelined 1DhOpcode 10h GfxrenderstatescissorenableScissor Rectangle Enable Mask 1 = Update 0 = Do Not Update 3DState16NP Non-pipelined 1ChOpcode 81h GfxrenderstatescissorrectangleinfoOpcode 83h Stipple PatternStipple Pattern Gfxrenderstateantialiasing Vertex Sequence Gfxrenderstateprovokingvtxpixelization RulePixelization Rule Mask Small Triangle Filter Enable MaskOpcode 85h GfxrenderstatedestbuffervariablesDest Buffer Format 0h = Any 8-bit Surface Drawing and Scissor Rectangles Programming Hints/RulesColor Calculator 255 256 Programming Notes Clock Control RegistersExample Programming Sequence DCLK2 DCLK0D-Display Clock 0 Divisor RegisterDCLK1D-Display Clock 1 Divisor Register DCLK2D-Display Clock 2 Divisor Register LCDCLKD-LCD Clock Divisor Register Post Divisor Select LCD Clock DCLK0DS-Display & LCD Clock Divisor Select RegisterReserved VCO Loop Divide LCD Clock VCO Loop Divide clock Post Divisor Select clockInternal DAC Enable PWRCLKC-Power Management and Miscellaneous Clock ControlOverlay Registers Comment Register/Instruction CategoryUpdating Register Values 15.1. OV0ADD-Overlay 0 Register Update Address RegisterDOV0STA-Display/Overlay 0 Status Register GAMC50-Gamma Correction Registers Gamma CorrectionGreen Blue RedThree times Mathematical Gamma Correction For OverlayLatch Address Gamma Correction Theory Of OperationGamma Hardware Implementation Format Alignment Memory Offset RegistersOverlay Buffer Pointer Registers OBUF0Y-Overlay Buffer 0 Y Pointer RegisterOBUF0U-Overlay Buffer 0 U Pointer Register OBUF1Y-Overlay Buffer 1 Y Pointer RegisterOBUF1U-Overlay Buffer 1 U Pointer Register OBUF0V-Overlay Buffer 0 V Pointer RegisterBit Descriptiont OBUF1V-Overlay Buffer 1 V Pointer Register Overlay Stride Registers15.4.2.1. OV0STRIDE-Overlay 0 Stride Register YRGBVPH-Y/RGB Vertical Phase Register Overlay Initial Phase RegistersHORZPH-Horizontal Phase Register UVVPH-UV Vertical Phase RegisterINITPH-Initial Phase Register DWINPOS-Destination Window Position Register Overlay Destination Window Position/Size RegistersDWINSZ-Destination Window Size Register SWID-Source Width Register Overlay Source Size RegistersSWIDQW-Source Width In QWords Register SHEIGHT-Source Height Register YRGBSCALE-Y/RGB Scale Factor Register Overlay Scale Factor RegistersUVSCALE-UV Scale Factor Register 15.4.7.1. OV0CLRC0-Overlay 0 Color Correction 0 Register Overlay Color Correction Registers15.4.7.2. OV0CLRC1-Overlay 0 Color Correction 1 Register DCLRKV-Destination Color Key Value Register Overlay Destination Color Key RegistersAlways Constant Alpha Blend Enable Destination Constant Alpha Blend EnableDCLRKM-Destination Color Key Mask Register SCLRKVH-Source Color Key Value High Register Overlay Source Color Key RegistersSCLRKM-Source Color Key Mask Register SCLRKVL-Source Color Key Value Low RegisterSource Constant Alpha Blend Enable 15.4.10.1. OV0CONF-Overlay Configuration Register Overlay Configuration Registers15.4.11. OV0CMD-Overlay Command Register Vertical Luminance Filter. Vertical Luminance Filter Vertical Chrominance Filter. Vertical Chrominance FilterSource Format Manual flip commandAutomatic flipping 297 AWINPOS-Alpha Blend Window Position Register Overlay Alpha Blend Window Position/Size RegistersAWINSZ-Alpha Blend Window Size Register Overlay Flip Instruction300 Instruction Control Registers Instruction, Memory, and Interrupt Control RegistersFENCE-Graphics Memory Fence Table Registers Fence Pitch Reserved for address bits 31 downtoTile walk Fence sizeNormal Invalidation Mechanism PGTBLCTL-Page Table Control RegisterPGTBLER-Page Table Error Register Error Type PGTBLERRMSK-Page Table Error Mask Register Display Page Table Error Mask Buffer Unit Page Table Error MaskCommand Streamer DMA Page Table Error Mask Overlay Page Table Error MaskIntel 810 Chipset and Intel815 Chipset Errata RINGBUF-Ring Buffer RegistersRing Buffer Valid ReservedDWord Description Offset HWSPGA-Hardware Status Page Address RegisterIPEHR-Instruction Parser Error Header Register debug IPEIR-Instruction Parser Error Identification Register debugINSTDONE-Instruction Stream Interface Done Register This read only register reports engine done signalsNOPID-NOP Identification Register Disable State Variable Updates INSTPM-Instruction Parser Mode RegisterINSTPS-Instruction Parser State Register debug Cscpr State Machine Command Parser ABBSTR-Active Batch Buffer Start Address Register debug BBPPTR-Batch Buffer Parser Pointer Register debugDMAFADD-DMA Engine Fetch Address debug ABBEND-Active Batch Buffer End Address Register debugCurrent DMA Address Reserved User of the DMA Engine Instruction Fifo Debug Mode MEMMODE-Memory Interface Mode Register debugReserved Host Graphics Prefetch Mode Graphics Address Translation ModeBit Definition For Interrupt Control Registers Interrupt Control Registers321 HWSTAM-Hardware Status Mask Register Interrupt Enables. See Table IER-Interrupt Enable RegisterInterrupt Identity. See. Table IIR-Interrupt Identity RegisterInterrupt Mask Bits. See. Table IMR-Interrupt Mask RegisterISR-Interrupt Status Register Table Error handling in Intel 815 Chipset Error Identity, Mask and Status RegistersTable Error Resetting the Page Table ErrorEMR-Error Mask Register EIR-Error Identity RegisterESR-Error Status Register FWBLC-FIFO Watermark and Burst Length Control Display Interface Control332 HTOTAL-Horizontal Total Register LCD / TV-Out Register DescriptionHBLANK-Horizontal Blank Register HSYNC-Horizontal Sync Register VTOTAL-Vertical Total Register VBLANK-Vertical Blank Register VSYNC-Vertical Sync Register LCDTVC-LCD/TV-Out Control Register LCD / TV-Out EnableSync Polarity Control Fphsync Control FP Vesa VGA ModeFP / 740 Data Ordering Fpvsync ControlActive Data Polarity Border EnableFphsync Output Control Active Data OrderBCLRPAT- Border Color Pattern Register OVRACT-Overlay Active RegisterDRT-DRAM Row Type Local Memory InterfaceBit RAS# act. To precharge t RAS Refresh to RAS# act. t RC Reserved Paging Mode Control PMCBit RAS#-to-CAS# delay t RCD DRAMCL-DRAM Control LowDRAMCH-DRAM Control High 346 HVSYNC-HSYNC/VSYNC Control Register 19. I/O Control RegistersHSYNC/VSYNC Control1916 GPIOAGeneral Purpose I/O Control Register a Gpio RegistersValue .bit GPIOBGeneral Purpose I/O Control Register B 351 352 DISPSL-Display Scan Line Count Display And Cursor RegistersLine Counter for Display Inclusive / Exclusive DISPSLC-Display Scan Line Count Range ComparePixel Pipeline Control PIXCONF-Pixel Pipeline ConfigurationReserved Display path Graphics Gamma Enable. See note Overlay path Gamma Enable. See noteCRT Overscan Color Display Color ModeBit DAC Enable Enable Extended Status Read ModeSWF13-Software Flag Registers GUI ModeTransition from VGA modes to hires mode or opposite BLTCNTL-BLT ControlDPLYBASE-Display Base Address Register DPLYSTAS-Display Status Select Register Reserved Flat Panel Hot Plug Detect EnableVertical Sync Status Enable Display Line Compare EnableVertical Sync Status Vertical Blank EnableOverlay Registers Upated Enable Overlay Registers Updated StatusCURCNTR-Cursor Control Register Hardware CursorReserved Cursor Coordinate System Origin Select CURPOS-Cursor Position Register CURBASE-Cursor Base Address RegisterAppendix a Mode Parameters Parameters for Screen Resolution/Refresh Rate 320x20070Hz = Parameters for Screen Resolution/Refresh Rate 320x24070Hz = Parameters for Screen Resolution/Refresh Rate 352X48070Hz = Parameters for Screen Resolution/Refresh Rate 352X57670Hz = Parameters for Screen Resolution/Refresh Rate 400x30070Hz = Parameters for Screen Resolution/Refresh Rate 512X38470Hz = Parameters for Screen Resolution/Refresh Rate 640x35085Hz = Parameters for Screen Resolution/Refresh Rate 640x40070Hz = Parameters for Screen Resolution/Refresh Rate 640x40085Hz = Parameters for Screen Resolution/Refresh Rate 640x48060Hz = Parameters for Screen Resolution/Refresh Rate 640x48070Hz = Parameters for Screen Resolution/Refresh Rate 640x48072Hz = Parameters for Screen Resolution/Refresh Rate 640x48075Hz = Parameters for Screen Resolution/Refresh Rate 640x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x40085Hz = Parameters for Screen Resolution/Refresh Rate 720x48060Hz = Parameters for Screen Resolution/Refresh Rate 720x48075Hz = Parameters for Screen Resolution/Refresh Rate 720x48085Hz = Parameters for Screen Resolution/Refresh Rate 720x57660Hz = Parameters for Screen Resolution/Refresh Rate 720x57675Hz = Parameters for Screen Resolution/Refresh Rate 720x57685Hz = Parameters for Screen Resolution/Refresh Rate 800x60056Hz = Parameters for Screen Resolution/Refresh Rate 800x60060Hz = Parameters for Screen Resolution/Refresh Rate 800x60070Hz = Parameters for Screen Resolution/Refresh Rate 800x60072Hz = Parameters for Screen Resolution/Refresh Rate 800x60075Hz = Parameters for Screen Resolution/Refresh Rate 800x60085Hz = Parameters for Screen Resolution/Refresh Rate 854X48060Hz = Parameters for Screen Resolution/Refresh Rate 854X48075Hz = Parameters for Screen Resolution/Refresh Rate 854X48085Hz = 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 Intel around the world